gpu: nvgpu: fix channel unbind sequence from TSG

We right now remove a channel from TSG list and disable all the channels in
TSG while removing a channel from TSG
With this sequence if any one channel in TSG is closed, rest of the channels
are set as timed out and cannot be used anymore

We need to fix this sequence as below to allow removing a channel from active
TSG so that rest of the channels can still be used

- disable all channels of TSG
- preempt TSG
- check if CTX_RELOAD is set if support is available
  if CTX_RELOAD is set on channel, it should be moved to some other channel
- check if FAULTED is set if support is available
- if NEXT is set on channel then it means channel is still active
  print out an error in this case for the time being until properly handled
- remove the channel from runlist
- remove channel from TSG list
- re-enable rest of the channels in TSG
- clean up the channel (same as regular channels)

Add below fifo operations to support checking channel status
g->ops.fifo.tsg_verify_status_ctx_reload
g->ops.fifo.tsg_verify_status_faulted

Define ops.fifo.tsg_verify_status_ctx_reload operation for gm20b/gp10b/gp106
as gm20b_fifo_tsg_verify_status_ctx_reload()
This API will check if channel to be released has CTX_RELOAD set, if yes
CTX_RELOAD needs to be moved to some other channel in TSG

Remove static from channel_gk20a_update_runlist() and export it

Bug 200327095

Change-Id: I0dd4be7c7e0b9b759389ec12c5a148a4b919d3e2
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1560637
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 3 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 4564b6e9..adc630e6 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -212,7 +212,7 @@ struct gpu_ops {
                 int (*load_ctxsw_ucode)(struct gk20a *g);
                 u32 (*get_gpc_tpc_mask)(struct gk20a *g, u32 gpc_index);
                 void (*set_gpc_tpc_mask)(struct gk20a *g, u32 gpc_index);
-                void (*free_channel_ctx)(struct channel_gk20a *c);
+                void (*free_channel_ctx)(struct channel_gk20a *c, bool is_tsg);
                 int (*alloc_obj_ctx)(struct channel_gk20a  *c,
                                 struct nvgpu_alloc_obj_ctx_args *args);
                 int (*bind_ctxsw_zcull)(struct gk20a *g, struct gr_gk20a *gr,
@@ -477,6 +477,8 @@ struct gpu_ops {
                 int (*preempt_tsg)(struct gk20a *g, u32 tsgid);
                 int (*enable_tsg)(struct tsg_gk20a *tsg);
                 int (*disable_tsg)(struct tsg_gk20a *tsg);
+                void (*tsg_verify_status_ctx_reload)(struct channel_gk20a *ch);
+                void (*tsg_verify_status_faulted)(struct channel_gk20a *ch);
                 int (*reschedule_runlist)(struct gk20a *g, u32 runlist_id);
                 int (*update_runlist)(struct gk20a *g, u32 runlist_id,
                                 u32 chid, bool add,