gpu: nvgpu: remove unused regops HALs

Below regops HALs are not being called from anywhere, so remove them
gops.regops.get_runcontrol_whitelist_ranges()
gops.regops.get_runcontrol_whitelist_ranges_count()
gops.regops.get_qctl_whitelist_ranges()
gops.regops.get_qctl_whitelist_ranges_count()

HAL gops.regops.apply_smpc_war() is unimplemented for all the chips, and it
was originally only needed for gk20a which is not unsupported
So remove this HAL and its call too

Jira NVGPU-620

Change-Id: Ia2c74883cd647a2e94ee740ffd040a40c442b939
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1813106
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 0 insertions, 7 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index fac7c5df..4d4b4cb1 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -1140,15 +1140,8 @@ struct gpu_ops {
                 u64 (*get_context_whitelist_ranges_count)(void);
                 const u32* (*get_runcontrol_whitelist)(void);
                 u64 (*get_runcontrol_whitelist_count)(void);
-                const struct regop_offset_range* (
-                                *get_runcontrol_whitelist_ranges)(void);
-                u64 (*get_runcontrol_whitelist_ranges_count)(void);
                 const u32* (*get_qctl_whitelist)(void);
                 u64 (*get_qctl_whitelist_count)(void);
-                const struct regop_offset_range* (
-                                *get_qctl_whitelist_ranges)(void);
-                u64 (*get_qctl_whitelist_ranges_count)(void);
-                int (*apply_smpc_war)(struct dbg_session_gk20a *dbg_s);
         } regops;
         struct {
                 void (*intr_mask)(struct gk20a *g);