gpu: nvgpu: Fix CWD floorsweep programming

Program CWD TPC and SM registers correctly. The old code did not work
when there are more than 4 TPCs.

Refactor init_fs_mask to reduce code duplication.

Change-Id: Id93c1f8df24f1b7ee60314c3204e288b91951a88
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1143697
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>

1 files changed, 4 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 8dfe8eda..5d06a441 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -260,6 +260,10 @@ struct gpu_ops {
                 int (*get_preemption_mode_flags)(struct gk20a *g,
                        struct nvgpu_preemption_modes_rec *preemption_modes_rec);
                 int (*fuse_override)(struct gk20a *g);
+                int (*load_smid_config)(struct gk20a *g);
+                void (*program_sm_id_numbering)(struct gk20a *g,
+                                                u32 gpc, u32 tpc, u32 smid);
+                void (*program_active_tpc_counts)(struct gk20a *g, u32 gpc);
         } gr;
         const char *name;
         struct {