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authorMayank Kaushik <mkaushik@nvidia.com>2014-09-25 20:21:24 -0400
committerDan Willemsen <dwillemsen@nvidia.com>2015-03-18 15:11:57 -0400
commit1ee103adf30c14efef932faedc6b1bb226f7139b (patch)
treececd392c75e937767ba2e4b211cbfe28bca1e926 /drivers/gpu/nvgpu/gk20a/gk20a.h
parentaec94d809348e8ff9a900c2a38456d7217c86728 (diff)
gpu: nvgpu: create a hal function for smpc war
Create a HAL function for applying the SMPC workaround.The workaround is only needed on gk20a, and not on gm20b. Change-Id: I9edc741df32ab7d1dad38ecc56f238828128bfef Signed-off-by: Mayank Kaushik <mkaushik@nvidia.com> Reviewed-on: http://git-master/r/539187 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.h')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index a111a040..28d43081 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -335,6 +335,7 @@ struct gpu_ops {
335 const struct regop_offset_range* ( 335 const struct regop_offset_range* (
336 *get_qctl_whitelist_ranges)(void); 336 *get_qctl_whitelist_ranges)(void);
337 int (*get_qctl_whitelist_ranges_count)(void); 337 int (*get_qctl_whitelist_ranges_count)(void);
338 int (*apply_smpc_war)(struct dbg_session_gk20a *dbg_s);
338 } regops; 339 } regops;
339 struct { 340 struct {
340 void (*intr_enable)(struct gk20a *g); 341 void (*intr_enable)(struct gk20a *g);