gpu: nvgpu: mask intr before gpu power off

once gpu is powered off i.e. power_on set to false, nvgpu isr
does not handle stall/nonstall irq. Depending upon state
of gpu, this can result in either of following errors:

1) irq 458: nobody cared (try booting with the "irqpoll" option)
2) "HSM ERROR 42, GPU" from SCE if it detects that an interrupt is
not in time.

Fix these by masking all interrupts just before gpu power off
as nvgpu won't be handling any irq anymore.

While masking interrupts, if there are any pending interrupts,
then report those with a log message.

Bug 1987855
Bug 200424832

Change-Id: I95b087f5c24d439e5da26c6e4fff74d8a525f291
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1770802
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 2 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 6d19d8a3..13c8928f 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -1119,6 +1119,7 @@ struct gpu_ops {
                 int (*apply_smpc_war)(struct dbg_session_gk20a *dbg_s);
         } regops;
         struct {
+                void (*intr_mask)(struct gk20a *g);
                 void (*intr_enable)(struct gk20a *g);
                 void (*intr_unit_config)(struct gk20a *g,
                                 bool enable, bool is_stalling, u32 unit);
@@ -1139,6 +1140,7 @@ struct gpu_ops {
                 void (*reset)(struct gk20a *g, u32 units);
                 u32 (*boot_0)(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev);
                 bool (*is_intr1_pending)(struct gk20a *g, enum nvgpu_unit unit, u32 mc_intr_1);
+                void (*log_pending_intrs)(struct gk20a *g);
         } mc;
         struct {
                 void (*show_dump)(struct gk20a *g,