gpu: nvgpu: add sm lock_down gr ops

Add lock_down_sm and wait_for_sm_lock_down gr ops
Required to support multiple SM and t19x SM register
address changes

JIRA GPUT19X-75

Change-Id: I529babde51d9b2143fe3740a4f67c582b7eb404b
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1514042
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 4 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index a0a67332..483cdd6e 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -296,6 +296,10 @@ struct gpu_ops {
                 u32 (*get_sm_hww_global_esr)(struct gk20a *g,
                                                 u32 gpc, u32 tpc, u32 sm);
                 u32 (*get_sm_no_lock_down_hww_global_esr_mask)(struct gk20a *g);
+                int  (*lock_down_sm)(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
+                                u32 global_esr_mask, bool check_errors);
+                int  (*wait_for_sm_lock_down)(struct gk20a *g, u32 gpc, u32 tpc,
+                                u32 sm, u32 global_esr_mask, bool check_errors);
                 void (*get_esr_sm_sel)(struct gk20a *g, u32 gpc, u32 tpc,
                                          u32 *esr_sm_sel);
                 int (*handle_sm_exception)(struct gk20a *g,