gpu: nvgpu: switch gk20a nonstall ops to #defines

Fix MISRA rule 10.1 violations involving gk20a_nonstall_ops
enums by replacing them with with corresponding #defines.

Because these values can be used in expressions that require
unsigned values (e.g. bitwise OR) we cannot use enums.

The g->ce2.isr_nonstall() function was previously returning an
int that was a combination of gk20a_nonstall_ops enum bits which
led to the violations.

JIRA NVGPU-650

Change-Id: I6210aacec8829b3c8d339c5fe3db2f3069c67406
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1796242
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 3 insertions, 5 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 5300f7dd..cf202f14 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -207,7 +207,7 @@ struct gpu_ops {
         } ltc;
         struct {
                 void (*isr_stall)(struct gk20a *g, u32 inst_id, u32 pri_base);
-                int (*isr_nonstall)(struct gk20a *g, u32 inst_id, u32 pri_base);
+                u32 (*isr_nonstall)(struct gk20a *g, u32 inst_id, u32 pri_base);
                 u32 (*get_num_pce)(struct gk20a *g);
         } ce2;
         struct {
@@ -1668,10 +1668,8 @@ struct gk20a_cyclestate_buffer_elem {
 };
 
 /* operations that will need to be executed on non stall workqueue */
-enum gk20a_nonstall_ops {
-        gk20a_nonstall_ops_wakeup_semaphore = BIT(0), /* wake up semaphore */
-        gk20a_nonstall_ops_post_events = BIT(1),
-};
+#define GK20A_NONSTALL_OPS_WAKEUP_SEMAPHORE     BIT32(0)
+#define GK20A_NONSTALL_OPS_POST_EVENTS          BIT32(1)
 
 /* register accessors */
 void __nvgpu_check_gpu_state(struct gk20a *g);