gpu: nvgpu: ioctls for clock controls

Add ioctls for clock range and VF points query.
Add ioctls to set target mhz, and get actual mhz.

Jira DNVGPU-125

Change-Id: I7639789bb15eabd8c98adc468201dba3a6e19ade
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1223473
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
(cherry picked from commit 5e635ae34221c99a739321bcfc1418db56c1051d)
Reviewed-on: http://git-master/r/1243107
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 10 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 024be4db..564026a4 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -56,6 +56,7 @@ struct acr_desc;
 #include "gm206/bios_gm206.h"
 #ifdef CONFIG_ARCH_TEGRA_18x_SOC
 #include "clk/clk.h"
+#include "clk/clk_arb.h"
 #include "perf/perf.h"
 #include "pmgr/pmgr.h"
 #include "therm/thrm.h"
@@ -632,6 +633,13 @@ struct gpu_ops {
                 int (*suspend_clk_support)(struct gk20a *g);
                 u32 (*get_crystal_clk_hz)(struct gk20a *g);
         } clk;
+        struct {
+                u32 (*get_arbiter_clk_domains)(struct gk20a *g);
+                int (*get_arbiter_clk_range)(struct gk20a *g, u32 api_domain,
+                                u16 *min_mhz, u16 *max_mhz);
+                int (*get_arbiter_clk_default)(struct gk20a *g, u32 api_domain,
+                                u16 *default_mhz);
+        } clk_arb;
         bool privsecurity;
         bool securegpccs;
         bool pmupstate;
@@ -956,6 +964,8 @@ struct gk20a {
         struct nvgpu_bios bios;
         struct debugfs_blob_wrapper bios_blob;
 
+        struct nvgpu_clk_arb *clk_arb;
+
         struct gk20a_ce_app ce_app;
 
         /* PCI device identifier */