gpu: nvgpu: add HAL to insert semaphore commands

Add below new HALs
gops.fifo.add_sema_cmd() to insert HOST semaphore acquire/release methods
gops.fifo.get_sema_wait_cmd_size() to get size of acquire command buffer
gops.fifo.get_sema_incr_cmd_size() to get size of release command buffer

Separate out new API gk20a_fifo_add_sema_cmd() to implement semaphore acquire/
release sequence and set it to gops.fifo.add_sema_cmd()

Add gk20a_fifo_get_sema_wait_cmd_size() and gk20a_fifo_get_sema_incr_cmd_size()
to return respective command buffer sizes

Jira NVGPUT-16

Change-Id: Ia81a50921a6a56ebc237f2f90b137268aaa2d749
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1704490
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 6 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 23e85ee9..17f662df 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -678,6 +678,12 @@ struct gpu_ops {
                         u32 count, u32 buffer_index);
                 int (*runlist_wait_pending)(struct gk20a *g, u32 runlist_id);
                 void (*ring_channel_doorbell)(struct channel_gk20a *c);
+                u32 (*get_sema_wait_cmd_size)(void);
+                u32 (*get_sema_incr_cmd_size)(void);
+                void (*add_sema_cmd)(struct gk20a *g,
+                        struct nvgpu_semaphore *s, u64 sema_va,
+                        struct priv_cmd_entry *cmd,
+                        u32 off, bool acquire, bool wfi);
         } fifo;
         struct pmu_v {
                 u32 (*get_pmu_cmdline_args_size)(struct nvgpu_pmu *pmu);