diff options
| author | Alex Frid <afrid@nvidia.com> | 2014-08-12 20:30:08 -0400 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:11:01 -0400 |
| commit | 9635e19e618b2897d27a21a240110289d424c99e (patch) | |
| tree | ac2938710a58b49b935398c7e3bacc2391f013a4 /drivers/gpu/nvgpu/gk20a/gk20a.c | |
| parent | b2b37c6437a5492f85a1d0f06358e576271d6e0d (diff) | |
gpu: nvgpu: Don't increase GPCPLL rate before bypass
Do not force GM20b GPCPLL post divider to 1:2 settings before switching
to bypass clock if PLL output frequency is increased as a result. Move
this step under bypass. However, this step is still needed in case when
PLL can be configured without switch to bypass.
Bug 1450787
Change-Id: Iab81b0e5a71f44f738a64e15b05df41fdbd61ebe
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/456505
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.c')
0 files changed, 0 insertions, 0 deletions