gpu: nvgpu: Add bus HAL

Add bus HAL and move all bus related hardware sequencing to that file:
BAR1 binding, timer access, and interrupt handling.

Change-Id: Ibc5f5797dc338de10749b446a7bdbcae600fecb4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1323353
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 2 insertions, 102 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c
index 76484dd5..72528758 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.c
@@ -57,6 +57,7 @@
 #include "hal.h"
 #include "vgpu/vgpu.h"
 #include "pci.h"
+#include "bus_gk20a.h"
 #ifdef CONFIG_ARCH_TEGRA_18x_SOC
 #include "pstate/pstate.h"
 #endif
@@ -70,11 +71,8 @@
 #endif
 
 #include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_timer_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_bus_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_top_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_ltc_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_gr_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_fb_gk20a.h>
 
 
@@ -330,42 +328,6 @@ static irqreturn_t gk20a_intr_isr_nonstall(int irq, void *dev_id)
         return g->ops.mc.isr_nonstall(g);
 }
 
-void gk20a_pbus_isr(struct gk20a *g)
-{
-        u32 val, err_code;
-        val = gk20a_readl(g, bus_intr_0_r());
-        if (val & (bus_intr_0_pri_squash_m() |
-                        bus_intr_0_pri_fecserr_m() |
-                        bus_intr_0_pri_timeout_m())) {
-                gk20a_dbg(gpu_dbg_intr, "pmc_enable : 0x%x",
-                        gk20a_readl(g, mc_enable_r()));
-                gk20a_dbg(gpu_dbg_intr, "NV_PBUS_INTR_0 : 0x%x", val);
-                gk20a_dbg(gpu_dbg_intr,
-                        "NV_PTIMER_PRI_TIMEOUT_SAVE_0: 0x%x\n",
-                        gk20a_readl(g, timer_pri_timeout_save_0_r()));
-                gk20a_dbg(gpu_dbg_intr,
-                        "NV_PTIMER_PRI_TIMEOUT_SAVE_1: 0x%x\n",
-                        gk20a_readl(g, timer_pri_timeout_save_1_r()));
-                err_code = gk20a_readl(g, timer_pri_timeout_fecs_errcode_r());
-                gk20a_dbg(gpu_dbg_intr,
-                        "NV_PTIMER_PRI_TIMEOUT_FECS_ERRCODE: 0x%x\n",
-                        err_code);
-                if (err_code == 0xbadf13)
-                        gk20a_dbg(gpu_dbg_intr,
-                        "NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC: 0x%x\n",
-                        gk20a_readl(g, gr_gpc0_fs_gpc_r()));
-
-                gk20a_writel(g, timer_pri_timeout_save_0_r(), 0);
-                gk20a_writel(g, timer_pri_timeout_save_1_r(), 0);
-        }
-
-        if (val)
-                gk20a_dbg(gpu_dbg_intr,
-                        "Unhandled pending pbus interrupt\n");
-
-        gk20a_writel(g, bus_intr_0_r(), val);
-}
-
 static irqreturn_t gk20a_intr_thread_stall(int irq, void *dev_id)
 {
         struct gk20a *g = dev_id;
@@ -596,13 +558,7 @@ int gk20a_pm_finalize_poweron(struct device *dev)
         if (err)
                 goto done;
 
-        if (!tegra_platform_is_silicon())
-                gk20a_writel(g, bus_intr_en_0_r(), 0x0);
-        else
-                gk20a_writel(g, bus_intr_en_0_r(),
-                                bus_intr_en_0_pri_squash_m() |
-                                bus_intr_en_0_pri_fecserr_m() |
-                                bus_intr_en_0_pri_timeout_m());
+        g->ops.bus.init_hw(g);
 
         if (g->ops.clk.disable_slowboot)
                 g->ops.clk.disable_slowboot(g);
@@ -630,22 +586,6 @@ int gk20a_pm_finalize_poweron(struct device *dev)
                 }
         }
 
-        /* enable pri timeout only on silicon */
-        if (tegra_platform_is_silicon()) {
-                gk20a_writel(g,
-                        timer_pri_timeout_r(),
-                        timer_pri_timeout_period_f(
-                                platform->default_pri_timeout ?
-                                        platform->default_pri_timeout :
-                                                                0x186A0) |
-                        timer_pri_timeout_en_en_enabled_f());
-        } else {
-                gk20a_writel(g,
-                        timer_pri_timeout_r(),
-                        timer_pri_timeout_period_f(0x186A0) |
-                        timer_pri_timeout_en_en_disabled_f());
-        }
-
         err = gk20a_init_fifo_reset_enable_hw(g);
         if (err) {
                 gk20a_err(dev, "failed to reset gk20a fifo");
@@ -1910,46 +1850,6 @@ int gk20a_init_gpu_characteristics(struct gk20a *g)
         return 0;
 }
 
-int gk20a_read_ptimer(struct gk20a *g, u64 *value)
-{
-        const unsigned int max_iterations = 3;
-        unsigned int i = 0;
-        u32 gpu_timestamp_hi_prev = 0;
-
-        if (!value)
-                return -EINVAL;
-
-        /* Note. The GPU nanosecond timer consists of two 32-bit
-         * registers (high & low). To detect a possible low register
-         * wrap-around between the reads, we need to read the high
-         * register before and after low. The wraparound happens
-         * approximately once per 4 secs. */
-
-        /* get initial gpu_timestamp_hi value */
-        gpu_timestamp_hi_prev = gk20a_readl(g, timer_time_1_r());
-
-        for (i = 0; i < max_iterations; ++i) {
-                u32 gpu_timestamp_hi = 0;
-                u32 gpu_timestamp_lo = 0;
-
-                gpu_timestamp_lo = gk20a_readl(g, timer_time_0_r());
-                gpu_timestamp_hi = gk20a_readl(g, timer_time_1_r());
-
-                if (gpu_timestamp_hi == gpu_timestamp_hi_prev) {
-                        *value = (((u64)gpu_timestamp_hi) << 32) |
-                                gpu_timestamp_lo;
-                        return 0;
-                }
-
-                /* wrap-around detected, retry */
-                gpu_timestamp_hi_prev = gpu_timestamp_hi;
-        }
-
-        /* too many iterations, bail out */
-        gk20a_err(dev_from_gk20a(g), "failed to read ptimer");
-        return -EBUSY;
-}
-
 /*
  * Free the gk20a struct.
  */