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authorNicolas Benech <nbenech@nvidia.com>2018-08-23 16:23:52 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-09-05 23:39:08 -0400
commit2eface802a4aea417206bcdda689a65cf47d300b (patch)
tree502af9d48004af4edf8f02a2a7cf751ef5a11325 /drivers/gpu/nvgpu/gk20a/flcn_gk20a.c
parentb44c7fdb114a63ab98fffc0f246776b56399ff64 (diff)
gpu: nvgpu: Fix mutex MISRA 17.7 violations
MISRA Rule-17.7 requires the return value of all functions to be used. Fix is either to use the return value or change the function to return void. This patch contains fix for calls to nvgpu_mutex_init and improves related error handling. JIRA NVGPU-677 Change-Id: I609fa138520cc7ccfdd5aa0e7fd28c8ca0b3a21c Signed-off-by: Nicolas Benech <nbenech@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1805598 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/flcn_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/flcn_gk20a.c20
1 files changed, 14 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c
index 2f715ae1..5fa4dd53 100644
--- a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c
@@ -707,9 +707,10 @@ void gk20a_falcon_ops(struct nvgpu_falcon *flcn)
707 gk20a_falcon_engine_dependency_ops(flcn); 707 gk20a_falcon_engine_dependency_ops(flcn);
708} 708}
709 709
710void gk20a_falcon_hal_sw_init(struct nvgpu_falcon *flcn) 710int gk20a_falcon_hal_sw_init(struct nvgpu_falcon *flcn)
711{ 711{
712 struct gk20a *g = flcn->g; 712 struct gk20a *g = flcn->g;
713 int err = 0;
713 714
714 switch (flcn->flcn_id) { 715 switch (flcn->flcn_id) {
715 case FALCON_ID_PMU: 716 case FALCON_ID_PMU:
@@ -726,28 +727,35 @@ void gk20a_falcon_hal_sw_init(struct nvgpu_falcon *flcn)
726 flcn->flcn_base = FALCON_FECS_BASE; 727 flcn->flcn_base = FALCON_FECS_BASE;
727 flcn->is_falcon_supported = true; 728 flcn->is_falcon_supported = true;
728 flcn->is_interrupt_enabled = false; 729 flcn->is_interrupt_enabled = false;
729 break; 730 break;
730 case FALCON_ID_GPCCS: 731 case FALCON_ID_GPCCS:
731 flcn->flcn_base = FALCON_GPCCS_BASE; 732 flcn->flcn_base = FALCON_GPCCS_BASE;
732 flcn->is_falcon_supported = true; 733 flcn->is_falcon_supported = true;
733 flcn->is_interrupt_enabled = false; 734 flcn->is_interrupt_enabled = false;
734 break; 735 break;
735 case FALCON_ID_NVDEC: 736 case FALCON_ID_NVDEC:
736 flcn->flcn_base = FALCON_NVDEC_BASE; 737 flcn->flcn_base = FALCON_NVDEC_BASE;
737 flcn->is_falcon_supported = false; 738 flcn->is_falcon_supported = false;
738 flcn->is_interrupt_enabled = false; 739 flcn->is_interrupt_enabled = false;
739 break; 740 break;
740 default: 741 default:
741 flcn->is_falcon_supported = false; 742 flcn->is_falcon_supported = false;
742 nvgpu_err(g, "Invalid flcn request"); 743 nvgpu_err(g, "Invalid flcn request");
744 err = -ENODEV;
743 break; 745 break;
744 } 746 }
745 747
746 if (flcn->is_falcon_supported) { 748 if (flcn->is_falcon_supported) {
747 nvgpu_mutex_init(&flcn->copy_lock); 749 err = nvgpu_mutex_init(&flcn->copy_lock);
748 gk20a_falcon_ops(flcn); 750 if (err != 0) {
751 nvgpu_err(g, "Error in flcn.copy_lock mutex initialization");
752 } else {
753 gk20a_falcon_ops(flcn);
754 }
749 } else { 755 } else {
750 nvgpu_log_info(g, "falcon 0x%x not supported on %s", 756 nvgpu_log_info(g, "falcon 0x%x not supported on %s",
751 flcn->flcn_id, g->name); 757 flcn->flcn_id, g->name);
752 } 758 }
759
760 return err;
753} 761}