diff options
author | Seema Khowala <seemaj@nvidia.com> | 2018-02-22 16:00:25 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-05-04 00:43:06 -0400 |
commit | c9463fdbb31324cc8eaa7fbed69f8d4b98ef38b5 (patch) | |
tree | c7b620761aff85eea584ed63573548fcd7d679c4 /drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | |
parent | bf0379997799e7f83514e974cd02aaaab85a4101 (diff) |
gpu: nvgpu: add rc_type i/p param to gk20a_fifo_recover
Add below rc_types to be passed to gk20a_fifo_recover
MMU_FAULT
PBDMA_FAULT
GR_FAULT
PREEMPT_TIMEOUT
CTXSW_TIMEOUT
RUNLIST_UPDATE_TIMEOUT
FORCE_RESET
SCHED_ERR
This is nice to have to know what triggered recovery.
Bug 2065990
Change-Id: I202268c5f237be2180b438e8ba027fce684967b6
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1662619
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/fifo_gk20a.h')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index c6d34945..c4f7f8ac 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | |||
@@ -57,10 +57,15 @@ enum { | |||
57 | 57 | ||
58 | #define GRFIFO_TIMEOUT_CHECK_PERIOD_US 100000 | 58 | #define GRFIFO_TIMEOUT_CHECK_PERIOD_US 100000 |
59 | 59 | ||
60 | #define RC_TYPE_NORMAL 0 | 60 | #define RC_TYPE_NO_RC 0 |
61 | #define RC_TYPE_MMU_FAULT 1 | 61 | #define RC_TYPE_MMU_FAULT 1 |
62 | #define RC_TYPE_PBDMA_FAULT 2 | 62 | #define RC_TYPE_PBDMA_FAULT 2 |
63 | #define RC_TYPE_NO_RC 0xff | 63 | #define RC_TYPE_GR_FAULT 3 |
64 | #define RC_TYPE_PREEMPT_TIMEOUT 4 | ||
65 | #define RC_TYPE_CTXSW_TIMEOUT 5 | ||
66 | #define RC_TYPE_RUNLIST_UPDATE_TIMEOUT 6 | ||
67 | #define RC_TYPE_FORCE_RESET 7 | ||
68 | #define RC_TYPE_SCHED_ERR 8 | ||
64 | 69 | ||
65 | #define NVGPU_FIFO_DEFAULT_TIMESLICE_TIMEOUT 128UL | 70 | #define NVGPU_FIFO_DEFAULT_TIMESLICE_TIMEOUT 128UL |
66 | #define NVGPU_FIFO_DEFAULT_TIMESLICE_SCALE 3UL | 71 | #define NVGPU_FIFO_DEFAULT_TIMESLICE_SCALE 3UL |
@@ -256,9 +261,11 @@ void gk20a_fifo_recover(struct gk20a *g, | |||
256 | u32 engine_ids, /* if zero, will be queried from HW */ | 261 | u32 engine_ids, /* if zero, will be queried from HW */ |
257 | u32 hw_id, /* if ~0, will be queried from HW */ | 262 | u32 hw_id, /* if ~0, will be queried from HW */ |
258 | bool hw_id_is_tsg, /* ignored if hw_id == ~0 */ | 263 | bool hw_id_is_tsg, /* ignored if hw_id == ~0 */ |
259 | bool id_is_known, bool verbose); | 264 | bool id_is_known, bool verbose, int rc_type); |
260 | void gk20a_fifo_recover_ch(struct gk20a *g, u32 chid, bool verbose); | 265 | void gk20a_fifo_recover_ch(struct gk20a *g, u32 chid, bool verbose, |
261 | void gk20a_fifo_recover_tsg(struct gk20a *g, u32 tsgid, bool verbose); | 266 | int rc_type); |
267 | void gk20a_fifo_recover_tsg(struct gk20a *g, u32 tsgid, bool verbose, | ||
268 | int rc_type); | ||
262 | int gk20a_fifo_force_reset_ch(struct channel_gk20a *ch, | 269 | int gk20a_fifo_force_reset_ch(struct channel_gk20a *ch, |
263 | u32 err_code, bool verbose); | 270 | u32 err_code, bool verbose); |
264 | void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id); | 271 | void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id); |