gpu: nvgpu: Read all fields of device_info

We were not using the engine_type field in device info, and the code
did not handle chained entries properly. The code assumed that first
entry is for graphics and second for CE, which is not always true.

Improve the code to go through all entries of device_info, and
preserve values across entries until we reach the last entry.
Only last entry triggers a write to fifo engine info.

There can also be multiple engines with same type, so accumulate
interrupts and reset ids from all of them.

As the code got fixed, now it reads the engine enum correctly from
hardware. We used to compare that against CE0, but we should compare
against CE2.

gk20a_fifo_reset_engine() uses wrong constants - it is passed a
internal numbering of engines, but it compares them against hardware
engine enum.

Change-Id: Ia59273921c602d2a090f7a5b1404afb0fca2532c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1147746
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>

1 files changed, 3 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
index c95ba71c..e795eba0 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
@@ -79,8 +79,8 @@ struct fifo_mmu_fault_info_gk20a {
 struct fifo_engine_info_gk20a {
         u32 engine_id;
         u32 runlist_id;
-        u32 intr_id;
-        u32 reset_id;
+        u32 intr_mask;
+        u32 reset_mask;
         u32 pbdma_id;
         struct fifo_pbdma_exception_info_gk20a pbdma_exception_info;
         struct fifo_engine_exception_info_gk20a engine_exception_info;
@@ -222,5 +222,6 @@ void gk20a_fifo_debugfs_init(struct device *dev);
 
 const char *gk20a_fifo_interleave_level_name(u32 interleave_level);
 
+int gk20a_fifo_engine_enum_from_type(struct gk20a *g, u32 engine_type);
 
 #endif /*__GR_GK20A_H__*/