gpu: nvgpu: add fifo ops for intr_0_error_mask

This change is required to support t19x mmu fault

Change-Id: I3953dcf02c71ace606ba81896e56ea98683eb2ca
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1313482
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 3 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
index 30d0caba..2de5e2d6 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
@@ -313,6 +313,7 @@ void gk20a_get_ch_runlist_entry(struct channel_gk20a *ch, u32 *runlist);
 
 u32 gk20a_userd_gp_get(struct gk20a *g, struct channel_gk20a *c);
 void gk20a_userd_gp_put(struct gk20a *g, struct channel_gk20a *c);
+
 bool gk20a_is_fault_engine_subid_gpc(struct gk20a *g, u32 engine_subid);
 #ifdef CONFIG_DEBUG_FS
 struct fifo_profile_gk20a *gk20a_fifo_profile_acquire(struct gk20a *g);
@@ -333,4 +334,6 @@ const char *gk20a_decode_pbdma_chan_eng_ctx_status(u32 index);
 
 struct channel_gk20a *gk20a_refch_from_inst_ptr(struct gk20a *g, u64 inst_ptr);
 
+u32 gk20a_fifo_intr_0_error_mask(struct gk20a *g);
+
 #endif /*__GR_GK20A_H__*/