diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2014-09-10 07:04:32 -0400 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:11:17 -0400 |
commit | 1c7dcfdeef3b0672317fca947cb2097e97c623a9 (patch) | |
tree | f5e9c6a843d3e0079f1a124d2b9ffc21bb7585b5 /drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | |
parent | 2f232348e686f92a6a34e5fa7b98884d4b48313b (diff) |
gpu: nvgpu: use TSG recover API
Use TSG specific API gk20a_fifo_recover_tsg() in following cases :
- IOCTL_CHANNEL_FORCE_RESET
to force reset a channel in TSG, reset all the channels
- handle pbdma intr
while resetting in case of pbdma intr, if channel is part of
TSG, recover entire TSG
- TSG preempt failure
when TSG preempt times out, use TSG recover API
Use preempt_tsg() API to preempt if channel is part of TSG
Add below two generic APIs which will take care of preempting/
recovering either of channel or TSG as required
gk20a_fifo_preempt()
gk20a_fifo_force_reset_ch()
Bug 1470692
Change-Id: I8d46e252af79136be85a9a2accf8b51bd924ca8c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/497875
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/fifo_gk20a.h')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index e7560e27..103f00a1 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | |||
@@ -147,6 +147,7 @@ void gk20a_fifo_nonstall_isr(struct gk20a *g); | |||
147 | 147 | ||
148 | int gk20a_fifo_preempt_channel(struct gk20a *g, u32 hw_chid); | 148 | int gk20a_fifo_preempt_channel(struct gk20a *g, u32 hw_chid); |
149 | int gk20a_fifo_preempt_tsg(struct gk20a *g, u32 tsgid); | 149 | int gk20a_fifo_preempt_tsg(struct gk20a *g, u32 tsgid); |
150 | int gk20a_fifo_preempt(struct gk20a *g, struct channel_gk20a *ch); | ||
150 | 151 | ||
151 | int gk20a_fifo_enable_engine_activity(struct gk20a *g, | 152 | int gk20a_fifo_enable_engine_activity(struct gk20a *g, |
152 | struct fifo_engine_info_gk20a *eng_info); | 153 | struct fifo_engine_info_gk20a *eng_info); |
@@ -164,6 +165,7 @@ bool gk20a_fifo_mmu_fault_pending(struct gk20a *g); | |||
164 | void gk20a_fifo_recover(struct gk20a *g, u32 engine_ids, bool verbose); | 165 | void gk20a_fifo_recover(struct gk20a *g, u32 engine_ids, bool verbose); |
165 | void gk20a_fifo_recover_ch(struct gk20a *g, u32 hw_chid, bool verbose); | 166 | void gk20a_fifo_recover_ch(struct gk20a *g, u32 hw_chid, bool verbose); |
166 | void gk20a_fifo_recover_tsg(struct gk20a *g, u32 tsgid, bool verbose); | 167 | void gk20a_fifo_recover_tsg(struct gk20a *g, u32 tsgid, bool verbose); |
168 | int gk20a_fifo_force_reset_ch(struct channel_gk20a *ch, bool verbose); | ||
167 | int gk20a_init_fifo_reset_enable_hw(struct gk20a *g); | 169 | int gk20a_init_fifo_reset_enable_hw(struct gk20a *g); |
168 | void gk20a_init_fifo(struct gpu_ops *gops); | 170 | void gk20a_init_fifo(struct gpu_ops *gops); |
169 | 171 | ||