gpu: nvgpu: get intr mask for an active_engine_id

This is needed for t19x during eng preempt done polling.
E.g. copy engine (CE) stall interrupt should not prevent GR
from finishing preemption. In order to check if current stall
interrupt is valid for the engine being polled for
preemption completion, function to provide engine
intr mask is needed. With this, polling code can make sure
there are no stall interrupts pending for the engine being
polled for preemption done. If stall interrupts
are pending for an engine, preemption will never finish.

Bug 200277163
Bug 1945121

Change-Id: Ie1ccac52c3e8d453a49084e195f2e7eaafb8f057
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1584065
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 11 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 424b1695..e65d3f00 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -463,6 +463,17 @@ int gk20a_fifo_init_engine_info(struct fifo_gk20a *f)
         return 0;
 }
 
+u32 gk20a_fifo_act_eng_interrupt_mask(struct gk20a *g, u32 act_eng_id)
+{
+        struct fifo_engine_info_gk20a *engine_info = NULL;
+
+        engine_info = gk20a_fifo_get_engine_info(g, act_eng_id);
+        if (engine_info)
+                return engine_info->intr_mask;
+
+        return 0;
+}
+
 u32 gk20a_fifo_engine_interrupt_mask(struct gk20a *g)
 {
         u32 eng_intr_mask = 0;