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authorKonsta Holtta <kholtta@nvidia.com>2014-10-03 03:45:23 -0400
committerDan Willemsen <dwillemsen@nvidia.com>2015-03-18 15:11:39 -0400
commiteab87c7afeb6ce55edcfeae568e6c3c4c0bd9f31 (patch)
treec196cfc790f40ba0d588d800e97e527db017a892 /drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
parent47caf9f7f5119c301c0690595c5e5f7318ddc595 (diff)
gpu: nvgpu: dump falcon stats in mmu fault handler
If engine status is in context switch in the fifo mmu fault handler, dump falcon stats and gr stats for each engine. Bug 1544766 Change-Id: Idfa9772b7e67072941144ac3bdd73e791fdc2b23 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/553205 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/fifo_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/fifo_gk20a.c22
1 files changed, 16 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 05377c3d..a9aea632 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -966,6 +966,7 @@ static bool gk20a_fifo_handle_mmu_fault(struct gk20a *g)
966 unsigned long engine_mmu_id; 966 unsigned long engine_mmu_id;
967 bool verbose = true; 967 bool verbose = true;
968 u32 grfifo_ctl; 968 u32 grfifo_ctl;
969
969 gk20a_dbg_fn(""); 970 gk20a_dbg_fn("");
970 971
971 g->fifo.deferred_reset_pending = false; 972 g->fifo.deferred_reset_pending = false;
@@ -1002,6 +1003,15 @@ static bool gk20a_fifo_handle_mmu_fault(struct gk20a *g)
1002 struct fifo_mmu_fault_info_gk20a f; 1003 struct fifo_mmu_fault_info_gk20a f;
1003 struct channel_gk20a *ch = NULL; 1004 struct channel_gk20a *ch = NULL;
1004 struct tsg_gk20a *tsg = NULL; 1005 struct tsg_gk20a *tsg = NULL;
1006 /* read and parse engine status */
1007 u32 status = gk20a_readl(g, fifo_engine_status_r(engine_id));
1008 u32 ctx_status = fifo_engine_status_ctx_status_v(status);
1009 bool ctxsw = (ctx_status ==
1010 fifo_engine_status_ctx_status_ctxsw_switch_v()
1011 || ctx_status ==
1012 fifo_engine_status_ctx_status_ctxsw_save_v()
1013 || ctx_status ==
1014 fifo_engine_status_ctx_status_ctxsw_load_v());
1005 1015
1006 get_exception_mmu_fault_info(g, engine_mmu_id, &f); 1016 get_exception_mmu_fault_info(g, engine_mmu_id, &f);
1007 trace_gk20a_mmu_fault(f.fault_hi_v, 1017 trace_gk20a_mmu_fault(f.fault_hi_v,
@@ -1023,14 +1033,14 @@ static bool gk20a_fifo_handle_mmu_fault(struct gk20a *g)
1023 f.fault_type_v, f.fault_type_desc, 1033 f.fault_type_v, f.fault_type_desc,
1024 f.fault_info_v, f.inst_ptr); 1034 f.fault_info_v, f.inst_ptr);
1025 1035
1036 if (ctxsw) {
1037 gk20a_fecs_dump_falcon_stats(g);
1038 gk20a_err(dev_from_gk20a(g), "gr_status_r : 0x%x",
1039 gk20a_readl(g, gr_status_r()));
1040 }
1041
1026 /* get the channel/TSG */ 1042 /* get the channel/TSG */
1027 if (fake_fault) { 1043 if (fake_fault) {
1028 /* read and parse engine status */
1029 u32 status = gk20a_readl(g,
1030 fifo_engine_status_r(engine_id));
1031 u32 ctx_status =
1032 fifo_engine_status_ctx_status_v(status);
1033
1034 /* use next_id if context load is failing */ 1044 /* use next_id if context load is failing */
1035 u32 id = (ctx_status == 1045 u32 id = (ctx_status ==
1036 fifo_engine_status_ctx_status_ctxsw_load_v()) ? 1046 fifo_engine_status_ctx_status_ctxsw_load_v()) ?