gpu: nvgpu: Program CE clock gating list after reset

Clock gating list for CE was programmed at GR init, but at that time
CE has not yet been brought out of reset. This causes a priv ring
error and the clock gating setting does not take place. Move
programming of CE clock gating list to CE initialization.

Bug 1846641

Change-Id: Ibc9fe2487408358304f80cd679d3b1ecac7cebe8
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1473301
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 0 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 4129e407..cb54a1ca 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -767,9 +767,6 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g)
         /* enable pmc pfifo */
         g->ops.mc.reset(g, mc_enable_pfifo_enabled_f());
 
-        if (g->ops.clock_gating.slcg_ce2_load_gating_prod)
-                g->ops.clock_gating.slcg_ce2_load_gating_prod(g,
-                                g->slcg_enabled);
         if (g->ops.clock_gating.slcg_fifo_load_gating_prod)
                 g->ops.clock_gating.slcg_fifo_load_gating_prod(g,
                                 g->slcg_enabled);