gpu: nvgpu: Set ch error before channel disable

In error case we first disabled the channel, and reset sync point to
max. After this we set channel error state. This causes a race if
channel is closed between setting sync point and setting channel
state.

Rearrange the code so that error state is set first, and only then
channel is disabled.

Bug 1519646

Change-Id: I20550f6a2708f892b6ba4ee714e90bdecdd128ad
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/418948
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>

1 files changed, 9 insertions, 9 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index f36a3eb6..2d09a840 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -1031,6 +1031,15 @@ static bool gk20a_fifo_handle_mmu_fault(struct gk20a *g)
                 }
 
                 if (ch) {
+                        /* check if engine reset should be deferred */
+                        if (gk20a_fifo_should_defer_engine_reset(g, engine_id, &f, fake_fault)) {
+                                g->fifo.mmu_fault_engines = fault_id;
+
+                                /* handled during channel free */
+                                g->fifo.deferred_reset_pending = true;
+                        } else
+                                verbose = gk20a_fifo_set_ctx_mmu_error(g, ch);
+
                         if (ch->in_use) {
                                 /* disable the channel from hw and increment
                                  * syncpoints */
@@ -1041,15 +1050,6 @@ static bool gk20a_fifo_handle_mmu_fault(struct gk20a *g)
                                           runlist->active_channels);
                         }
 
-                        /* check if engine reset should be deferred */
-                        if (gk20a_fifo_should_defer_engine_reset(g, engine_id, &f, fake_fault)) {
-                                g->fifo.mmu_fault_engines = fault_id;
-
-                                /* handled during channel free */
-                                g->fifo.deferred_reset_pending = true;
-                        } else
-                                verbose = gk20a_fifo_set_ctx_mmu_error(g, ch);
-
                 } else if (f.inst_ptr ==
                                 g->mm.bar1.inst_block.cpu_pa) {
                         gk20a_err(dev_from_gk20a(g), "mmu fault from bar1");