gpu: nvgpu: Clear FIFO intr before processing finished jobs

Clear the FIFO interrupt before prcessing the job list after
receiving a nonstalling interrupt. This prevents a race in which
some non-stalling interrupts after a semaphore incr can get lost.

Bug 1732449
JIRA DNVGPU-12

Change-Id: I03df56b2ebca4ed8a0aeb26dd5480c91ffb42d8b
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1133791
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 3 insertions, 8 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index e69fb288..66dfa48a 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -1738,13 +1738,6 @@ static u32 gk20a_fifo_handle_pbdma_intr(struct device *dev,
         return handled;
 }
 
-static u32 fifo_channel_isr(struct gk20a *g, u32 fifo_intr)
-{
-        gk20a_channel_semaphore_wakeup(g, false);
-        return fifo_intr_0_channel_intr_pending_f();
-}
-
-
 static u32 fifo_pbdma_isr(struct gk20a *g, u32 fifo_intr)
 {
         struct device *dev = dev_from_gk20a(g);
@@ -1810,10 +1803,12 @@ void gk20a_fifo_nonstall_isr(struct gk20a *g)
         gk20a_dbg(gpu_dbg_intr, "fifo nonstall isr %08x\n", fifo_intr);
 
         if (fifo_intr & fifo_intr_0_channel_intr_pending_f())
-                clear_intr |= fifo_channel_isr(g, fifo_intr);
+                clear_intr = fifo_intr_0_channel_intr_pending_f();
 
         gk20a_writel(g, fifo_intr_0_r(), clear_intr);
 
+        gk20a_channel_semaphore_wakeup(g, false);
+
         return;
 }