gpu: nvgpu: remove access to mc_enable_pb_r()

We don't need to configure mc_enable_pb_r() register in any of the supported
chips, so remove access to this register

Jira NVGPUT-52

Change-Id: I8a7a524367ce7953f926143242c6d63bc8fd5ed1
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1711245
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 0 insertions, 6 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index cc63c3b8..0c3e8039 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -796,12 +796,6 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g)
                 g->ops.clock_gating.blcg_fifo_load_gating_prod(g,
                                 g->blcg_enabled);
 
-        /* enable pbdma */
-        mask = 0;
-        for (i = 0; i < host_num_pbdma; ++i)
-                mask |= mc_enable_pb_sel_f(mc_enable_pb_0_enabled_v(), i);
-        gk20a_writel(g, mc_enable_pb_r(), mask);
-
         timeout = gk20a_readl(g, fifo_fb_timeout_r());
         timeout = set_field(timeout, fifo_fb_timeout_period_m(),
                         fifo_fb_timeout_period_max_f());