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author | seshendra Gadagottu <sgadagottu@nvidia.com> | 2017-03-17 14:30:57 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-05-26 17:07:12 -0400 |
commit | c0822cb22e13204e06b145ae950a33d45e95918e (patch) | |
tree | 1623fcd5db0d24190e6d93287742c8d2fee14794 /drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |
parent | e21e6e947b334cd16cc92c41953bf3c0153b1508 (diff) |
gpu: nvgpu: add chip specific sync point support
Added support for chip specific sync point implementation.
Relevant fifo hal functions are added and updated for
legacy chips.
JIRA GPUT19X-2
Change-Id: I9a9c36d71e15c384b5e5af460cd52012f94e0b04
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1258232
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/fifo_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 83 |
1 files changed, 83 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 05c13374..b8ff84df 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -4265,6 +4265,79 @@ u32 gk20a_fifo_pbdma_acquire_val(u64 timeout) | |||
4265 | return val; | 4265 | return val; |
4266 | } | 4266 | } |
4267 | 4267 | ||
4268 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | ||
4269 | void gk20a_fifo_add_syncpt_wait_cmd(struct gk20a *g, | ||
4270 | struct priv_cmd_entry *cmd, u32 off, | ||
4271 | u32 id, u32 thresh, u64 gpu_va) | ||
4272 | { | ||
4273 | gk20a_dbg_fn(""); | ||
4274 | |||
4275 | off = cmd->off + off; | ||
4276 | /* syncpoint_a */ | ||
4277 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001C); | ||
4278 | /* payload */ | ||
4279 | nvgpu_mem_wr32(g, cmd->mem, off++, thresh); | ||
4280 | /* syncpoint_b */ | ||
4281 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001D); | ||
4282 | /* syncpt_id, switch_en, wait */ | ||
4283 | nvgpu_mem_wr32(g, cmd->mem, off++, (id << 8) | 0x10); | ||
4284 | } | ||
4285 | |||
4286 | u32 gk20a_fifo_get_syncpt_wait_cmd_size(void) | ||
4287 | { | ||
4288 | return 4; | ||
4289 | } | ||
4290 | |||
4291 | void gk20a_fifo_add_syncpt_incr_cmd(struct gk20a *g, | ||
4292 | bool wfi_cmd, struct priv_cmd_entry *cmd, | ||
4293 | u32 id, u64 gpu_va) | ||
4294 | { | ||
4295 | u32 off = cmd->off; | ||
4296 | |||
4297 | gk20a_dbg_fn(""); | ||
4298 | if (wfi_cmd) { | ||
4299 | /* wfi */ | ||
4300 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001E); | ||
4301 | /* handle, ignored */ | ||
4302 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x00000000); | ||
4303 | } | ||
4304 | /* syncpoint_a */ | ||
4305 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001C); | ||
4306 | /* payload, ignored */ | ||
4307 | nvgpu_mem_wr32(g, cmd->mem, off++, 0); | ||
4308 | /* syncpoint_b */ | ||
4309 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001D); | ||
4310 | /* syncpt_id, incr */ | ||
4311 | nvgpu_mem_wr32(g, cmd->mem, off++, (id << 8) | 0x1); | ||
4312 | /* syncpoint_b */ | ||
4313 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001D); | ||
4314 | /* syncpt_id, incr */ | ||
4315 | nvgpu_mem_wr32(g, cmd->mem, off++, (id << 8) | 0x1); | ||
4316 | |||
4317 | } | ||
4318 | |||
4319 | u32 gk20a_fifo_get_syncpt_incr_cmd_size(bool wfi_cmd) | ||
4320 | { | ||
4321 | if (wfi_cmd) | ||
4322 | return 8; | ||
4323 | else | ||
4324 | return 6; | ||
4325 | } | ||
4326 | |||
4327 | void gk20a_fifo_free_syncpt_buf(struct channel_gk20a *c, | ||
4328 | struct nvgpu_mem *syncpt_buf) | ||
4329 | { | ||
4330 | |||
4331 | } | ||
4332 | |||
4333 | int gk20a_fifo_alloc_syncpt_buf(struct channel_gk20a *c, | ||
4334 | u32 syncpt_id, struct nvgpu_mem *syncpt_buf) | ||
4335 | { | ||
4336 | return 0; | ||
4337 | } | ||
4338 | #endif | ||
4339 | |||
4340 | |||
4268 | void gk20a_init_fifo(struct gpu_ops *gops) | 4341 | void gk20a_init_fifo(struct gpu_ops *gops) |
4269 | { | 4342 | { |
4270 | gops->fifo.disable_channel = gk20a_fifo_disable_channel; | 4343 | gops->fifo.disable_channel = gk20a_fifo_disable_channel; |
@@ -4312,4 +4385,14 @@ void gk20a_init_fifo(struct gpu_ops *gops) | |||
4312 | gops->fifo.teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg; | 4385 | gops->fifo.teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg; |
4313 | gops->fifo.handle_sched_error = gk20a_fifo_handle_sched_error; | 4386 | gops->fifo.handle_sched_error = gk20a_fifo_handle_sched_error; |
4314 | gops->fifo.handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0; | 4387 | gops->fifo.handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0; |
4388 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | ||
4389 | gops->fifo.alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf; | ||
4390 | gops->fifo.free_syncpt_buf = gk20a_fifo_free_syncpt_buf; | ||
4391 | gops->fifo.add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd; | ||
4392 | gops->fifo.get_syncpt_wait_cmd_size = | ||
4393 | gk20a_fifo_get_syncpt_wait_cmd_size; | ||
4394 | gops->fifo.add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd; | ||
4395 | gops->fifo.get_syncpt_incr_cmd_size = | ||
4396 | gk20a_fifo_get_syncpt_incr_cmd_size; | ||
4397 | #endif | ||
4315 | } | 4398 | } |