gpu: nvgpu: Add wrapper over atomic_t and atomic64_t

- added wrapper structs nvgpu_atomic_t and nvgpu_atomic64_t over
  atomic_t and atomic64_t
- added nvgpu_atomic_* and nvgpu_atomic64_* APIs to access the above
  wrappers.

JIRA NVGPU-121

Change-Id: I61667bb0a84c2fc475365abb79bffb42b8b4786a
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1533044
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit

1 files changed, 3 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index abd455d7..47e7d82e 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -3439,7 +3439,7 @@ void gk20a_dump_channel_status_ramfc(struct gk20a *g,
                 gk20a_debug_output(o, "SEMA STATE: value: 0x%08x "
                                    "next_val: 0x%08x addr: 0x%010llx\n",
                                    __nvgpu_semaphore_read(hw_sema),
-                                   atomic_read(&hw_sema->next_value),
+                                   nvgpu_atomic_read(&hw_sema->next_value),
                                    nvgpu_hw_sema_addr(hw_sema));
 
 #ifdef CONFIG_TEGRA_GK20A_NVHOST
@@ -3489,7 +3489,7 @@ void gk20a_debug_dump_all_channel_status_ramfc(struct gk20a *g,
                         continue;
 
                 ch_state[chid]->pid = ch->pid;
-                ch_state[chid]->refs = atomic_read(&ch->ref_count);
+                ch_state[chid]->refs = nvgpu_atomic_read(&ch->ref_count);
                 ch_state[chid]->deterministic = ch->deterministic;
                 nvgpu_mem_rd_n(g, &ch->inst_block, 0,
                                 &ch_state[chid]->inst_block[0],
@@ -3591,7 +3591,7 @@ void gk20a_fifo_channel_unbind(struct channel_gk20a *ch_gk20a)
 
         gk20a_dbg_fn("");
 
-        if (atomic_cmpxchg(&ch_gk20a->bound, true, false)) {
+        if (nvgpu_atomic_cmpxchg(&ch_gk20a->bound, true, false)) {
                 gk20a_writel(g, ccsr_channel_inst_r(ch_gk20a->chid),
                         ccsr_channel_inst_ptr_f(0) |
                         ccsr_channel_inst_bind_false_f());