gpu: nvgpu: IOCTL to set TSG timeslice

Add new IOCTL NVGPU_IOCTL_TSG_SET_PRIORITY to allow
setting timeslice for entire TSG

Return error from channel specific IOCTL_CHANNEL_SET_PRIORITY
if the channel is part of TSG

Separate out API gk20a_channel_get_timescale_from_timeslice()
to get timeslice_timeout and scale from timeslice period

Use this API to get timeslice_timeout and scale for TSG and
store it in tsg_gk20a structure

Then trigger runlist update so that new timeslice values
will be re-written to runlist for TSG

Bug 200146615

Change-Id: I555467d034f81b372b31372f0835d72b1c159508
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/824206
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 27 insertions, 8 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 39cb1174..5eba9f12 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -2115,6 +2115,32 @@ static int gk20a_fifo_runlist_wait_pending(struct gk20a *g, u32 runlist_id)
         return ret;
 }
 
+static inline u32 gk20a_get_tsg_runlist_entry_0(struct tsg_gk20a *tsg)
+{
+        u32 runlist_entry_0 = 0;
+
+        if (tsg->timeslice_timeout)
+                runlist_entry_0 = ram_rl_entry_id_f(tsg->tsgid) |
+                        ram_rl_entry_type_f(ram_rl_entry_type_tsg_f()) |
+                        ram_rl_entry_timeslice_scale_f(
+                                tsg->timeslice_scale) |
+                        ram_rl_entry_timeslice_timeout_f(
+                                tsg->timeslice_timeout) |
+                        ram_rl_entry_tsg_length_f(
+                                tsg->num_active_channels);
+        else
+                runlist_entry_0 = ram_rl_entry_id_f(tsg->tsgid) |
+                        ram_rl_entry_type_f(ram_rl_entry_type_tsg_f()) |
+                        ram_rl_entry_timeslice_scale_f(
+                                ram_rl_entry_timeslice_scale_3_f()) |
+                        ram_rl_entry_timeslice_timeout_f(
+                               ram_rl_entry_timeslice_timeout_128_f()) |
+                        ram_rl_entry_tsg_length_f(
+                                tsg->num_active_channels);
+
+        return runlist_entry_0;
+}
+
 static int gk20a_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id,
                                             u32 hw_chid, bool add,
                                             bool wait_for_finish)
@@ -2201,14 +2227,7 @@ static int gk20a_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id,
                         tsg = &f->tsg[tsgid];
                         /* add TSG entry */
                         gk20a_dbg_info("add TSG %d to runlist", tsg->tsgid);
-                        runlist_entry[0] = ram_rl_entry_id_f(tsg->tsgid) |
-                                ram_rl_entry_type_f(ram_rl_entry_type_tsg_f()) |
-                                ram_rl_entry_timeslice_scale_f(
-                                        ram_rl_entry_timeslice_scale_3_f()) |
-                                ram_rl_entry_timeslice_timeout_f(
-                                       ram_rl_entry_timeslice_timeout_128_f()) |
-                                ram_rl_entry_tsg_length_f(
-                                        tsg->num_active_channels);
+                        runlist_entry[0] = gk20a_get_tsg_runlist_entry_0(tsg);
                         runlist_entry[1] = 0;
                         runlist_entry += 2;
                         count++;