diff options
author | Thomas Fleury <tfleury@nvidia.com> | 2018-03-07 12:23:53 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-03-13 03:04:16 -0400 |
commit | 6c33a010d8e3983cc3504e073cd552f952440aa1 (patch) | |
tree | c86e364d468320c8b347b58b6a711f773b97ae42 /drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |
parent | f94c9d19c19883ca2b60acb8a000b34b32da0aa7 (diff) |
gpu: nvgpu: add placeholder for IPA to PA
Add __nvgpu_sgl_phys function that can be used to implement IPA
to PA translation in a subsequent change.
Adapt existing function prototypes to add pointer to gpu context,
as we will need to check if IPA to PA translation is needed.
JIRA EVLR-2442
Bug 200392719
Change-Id: I5a734c958c8277d1bf673c020dafb31263f142d6
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1673142
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/fifo_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 0def724d..5bd4dc57 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -867,6 +867,7 @@ static int gk20a_init_fifo_setup_sw(struct gk20a *g) | |||
867 | struct fifo_gk20a *f = &g->fifo; | 867 | struct fifo_gk20a *f = &g->fifo; |
868 | unsigned int chid, i; | 868 | unsigned int chid, i; |
869 | int err = 0; | 869 | int err = 0; |
870 | u64 userd_base; | ||
870 | 871 | ||
871 | gk20a_dbg_fn(""); | 872 | gk20a_dbg_fn(""); |
872 | 873 | ||
@@ -929,9 +930,9 @@ static int gk20a_init_fifo_setup_sw(struct gk20a *g) | |||
929 | } | 930 | } |
930 | gk20a_dbg(gpu_dbg_map, "userd gpu va = 0x%llx", f->userd.gpu_va); | 931 | gk20a_dbg(gpu_dbg_map, "userd gpu va = 0x%llx", f->userd.gpu_va); |
931 | 932 | ||
933 | userd_base = nvgpu_mem_get_addr(g, &f->userd); | ||
932 | for (chid = 0; chid < f->num_channels; chid++) { | 934 | for (chid = 0; chid < f->num_channels; chid++) { |
933 | f->channel[chid].userd_iova = | 935 | f->channel[chid].userd_iova = userd_base + |
934 | nvgpu_mem_get_addr(g, &f->userd) + | ||
935 | chid * f->userd_entry_size; | 936 | chid * f->userd_entry_size; |
936 | f->channel[chid].userd_gpu_va = | 937 | f->channel[chid].userd_gpu_va = |
937 | f->userd.gpu_va + chid * f->userd_entry_size; | 938 | f->userd.gpu_va + chid * f->userd_entry_size; |