gpu: nvgpu: Remove MC accesses from gk20a.c

Clean up gk20a.c by removing direct accesses to MC and moving the
accesses to happen via MC HAL.

The chip detection logic has to violate the HAL and call gk20a
version directly, because HAL ops cannot be set up before chip has
been identified.

Change-Id: I4cdd0ef3fcf7d3b561a3fca4247a8356fe8d18e1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1321576
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 2 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 8f7a2e22..6c4f12df 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -766,7 +766,7 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g)
 
         gk20a_dbg_fn("");
         /* enable pmc pfifo */
-        gk20a_reset(g, mc_enable_pfifo_enabled_f());
+        g->ops.mc.reset(g, mc_enable_pfifo_enabled_f());
 
         if (g->ops.clock_gating.slcg_ce2_load_gating_prod)
                 g->ops.clock_gating.slcg_ce2_load_gating_prod(g,
@@ -1249,7 +1249,7 @@ void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id)
         }
         if ((engine_enum == ENGINE_GRCE_GK20A) ||
                 (engine_enum == ENGINE_ASYNC_CE_GK20A)) {
-                        gk20a_reset(g, engine_info->reset_mask);
+                        g->ops.mc.reset(g, engine_info->reset_mask);
         }
 }