gpu: nvgpu: Move ctxsw_trace_gk20a.c to common/linux

Migrate ctxsw_trace_gk20a.c to common/linux/ctxsw_trace.c. This
has been done becasue the ctxsw tracing code is currently too
tightly tied to the Linux OS due to usage of a couple system calls:

  - poll()
  - mmap()

And general Linux driver framework code. As a result pulling the
logic out of the FECS tracing code is simply too large a scope for
time time being.

Instead the code was just copied as much as possible. The HAL ops
for the FECS code was hidden behind the FECS tracing config so
that the vm_area_struct is not used when QNX does not define said
config. All other non-HAL functions called by the FECS ctxsw
tracing code ha now also been hidden by this config. This is not
pretty but for the time being it seems like the way to go.

JIRA NVGPU-287

Change-Id: Ib880ab237f4abd330dc66998692c86c4507149c2
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1586547
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 19 insertions, 8 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index d10af9e9..17ae626b 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -1228,16 +1228,24 @@ void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id)
                         if (nvgpu_pmu_disable_elpg(g))
                                 nvgpu_err(g, "failed to set disable elpg");
                 }
-                /* resetting engine will alter read/write index.
-                 * need to flush circular buffer before re-enabling FECS.
+
+#ifdef CONFIG_GK20A_CTXSW_TRACE
+                /*
+                 * Resetting engine will alter read/write index. Need to flush
+                 * circular buffer before re-enabling FECS.
                  */
                 if (g->ops.fecs_trace.reset)
                         g->ops.fecs_trace.reset(g);
-                /*HALT_PIPELINE method, halt GR engine*/
+#endif
+
+                /* HALT_PIPELINE method, halt GR engine. */
                 if (gr_gk20a_halt_pipe(g))
                         nvgpu_err(g, "failed to HALT gr pipe");
-                /* resetting engine using mc_enable_r() is not
-                enough, we do full init sequence */
+
+                /*
+                 * Resetting engine using mc_enable_r() is not enough; we must
+                 * do full init sequence.
+                 */
                 gk20a_gr_reset(g);
                 if (g->support_pmu && g->can_elpg)
                         nvgpu_pmu_enable_elpg(g);
@@ -1618,6 +1626,8 @@ static bool gk20a_fifo_handle_mmu_fault(
                                 }
                         }
                 }
+
+#ifdef CONFIG_GK20A_CTXSW_TRACE
                 /*
                  * For non fake mmu fault, both tsg and ch pointers
                  * could be valid. Check tsg first.
@@ -1626,10 +1636,11 @@ static bool gk20a_fifo_handle_mmu_fault(
                         gk20a_ctxsw_trace_tsg_reset(g, tsg);
                 else if (ch)
                         gk20a_ctxsw_trace_channel_reset(g, ch);
+#endif
 
-                /* disable the channel/TSG from hw and increment
-                 * syncpoints */
-
+                /*
+                 * Disable the channel/TSG from hw and increment syncpoints.
+                 */
                 if (tsg) {
                         if (!g->fifo.deferred_reset_pending) {
                                 if (!fake_fault)