diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-03-09 01:18:36 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-04-12 18:33:44 -0400 |
commit | 3867db86bce819901e566ac46ea5cd1ead3dad11 (patch) | |
tree | 0ed3711ceabc0f9a5971507151ac446545ccfc90 /drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |
parent | 4c5feb1f72bb078c9002b91f15dd5474bb774b58 (diff) |
gpu: nvgpu: fifo ops for handling sched error and ctxsw timeout
For t19x, ctxsw timeout is not handled as part of fifo sched error
interrupt. A new fifo interrupt, ctxsw_timeout is added.
Bug 1856152
JIRA GPUT19X-74
Change-Id: I5a2ed15d967e5b14fbbb51b074080f1562bca84c
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1317599
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/fifo_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 08066604..c32c47fb 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -2051,7 +2051,7 @@ static bool gk20a_fifo_check_ch_ctxsw_timeout(struct channel_gk20a *ch, | |||
2051 | return recover; | 2051 | return recover; |
2052 | } | 2052 | } |
2053 | 2053 | ||
2054 | static bool gk20a_fifo_check_tsg_ctxsw_timeout(struct tsg_gk20a *tsg, | 2054 | bool gk20a_fifo_check_tsg_ctxsw_timeout(struct tsg_gk20a *tsg, |
2055 | bool *verbose, u32 *ms) | 2055 | bool *verbose, u32 *ms) |
2056 | { | 2056 | { |
2057 | struct channel_gk20a *ch; | 2057 | struct channel_gk20a *ch; |
@@ -2121,7 +2121,7 @@ static bool gk20a_fifo_check_tsg_ctxsw_timeout(struct tsg_gk20a *tsg, | |||
2121 | return recover; | 2121 | return recover; |
2122 | } | 2122 | } |
2123 | 2123 | ||
2124 | static bool gk20a_fifo_handle_sched_error(struct gk20a *g) | 2124 | bool gk20a_fifo_handle_sched_error(struct gk20a *g) |
2125 | { | 2125 | { |
2126 | u32 sched_error; | 2126 | u32 sched_error; |
2127 | u32 engine_id; | 2127 | u32 engine_id; |
@@ -2205,7 +2205,7 @@ static u32 fifo_error_isr(struct gk20a *g, u32 fifo_intr) | |||
2205 | } | 2205 | } |
2206 | 2206 | ||
2207 | if (fifo_intr & fifo_intr_0_sched_error_pending_f()) { | 2207 | if (fifo_intr & fifo_intr_0_sched_error_pending_f()) { |
2208 | print_channel_reset_log = gk20a_fifo_handle_sched_error(g); | 2208 | print_channel_reset_log = g->ops.fifo.handle_sched_error(g); |
2209 | handled |= fifo_intr_0_sched_error_pending_f(); | 2209 | handled |= fifo_intr_0_sched_error_pending_f(); |
2210 | } | 2210 | } |
2211 | 2211 | ||
@@ -2463,6 +2463,9 @@ void gk20a_fifo_isr(struct gk20a *g) | |||
2463 | if (fifo_intr & fifo_intr_0_pbdma_intr_pending_f()) | 2463 | if (fifo_intr & fifo_intr_0_pbdma_intr_pending_f()) |
2464 | clear_intr |= fifo_pbdma_isr(g, fifo_intr); | 2464 | clear_intr |= fifo_pbdma_isr(g, fifo_intr); |
2465 | 2465 | ||
2466 | if (g->ops.fifo.handle_ctxsw_timeout) | ||
2467 | g->ops.fifo.handle_ctxsw_timeout(g, fifo_intr); | ||
2468 | |||
2466 | if (unlikely(fifo_intr & error_intr_mask)) | 2469 | if (unlikely(fifo_intr & error_intr_mask)) |
2467 | clear_intr = fifo_error_isr(g, fifo_intr); | 2470 | clear_intr = fifo_error_isr(g, fifo_intr); |
2468 | 2471 | ||
@@ -4273,4 +4276,5 @@ void gk20a_init_fifo(struct gpu_ops *gops) | |||
4273 | gops->fifo.userd_gp_put = gk20a_fifo_userd_gp_put; | 4276 | gops->fifo.userd_gp_put = gk20a_fifo_userd_gp_put; |
4274 | gops->fifo.pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val; | 4277 | gops->fifo.pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val; |
4275 | gops->fifo.teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg; | 4278 | gops->fifo.teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg; |
4279 | gops->fifo.handle_sched_error = gk20a_fifo_handle_sched_error; | ||
4276 | } | 4280 | } |