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authorDeepak Nibade <dnibade@nvidia.com>2018-02-26 06:31:41 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2018-03-01 16:53:31 -0500
commit37a15ce818244ec11dbe002350d013cb636e0a9d (patch)
tree05f925962dd86c37d61b27f1eac026419a9ec22b /drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
parentdf2100018db1dba730937fe76464a8edf8ebf5dc (diff)
gpu: nvgpu: skip channel abort for deferred reset
In case deferred_reset_pending is set in gk20a_fifo_handle_mmu_fault() and in gv11b_fifo_teardown_ch_tsg(), we skip resetting the engines and skip setting the error notifier Then we call gk20a_channel_abort()/gk20a_fifo_abort_tsg() which aborts the channels, and resets the syncpoint values to release all the waiters But since we don't set error notifier this could lead User to assume a successful submission without any error To fix this disable channel/TSG in case deferred_reset_pending is set and skip calls to gk20a_channel_abort()/gk20a_fifo_abort_tsg() Note that we finally abort the channel when channel is being closed Bug 200363077 Change-Id: Ia48ca369701c14d1913d8f7b66ed466b7b840224 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1664319 (cherry picked from commit ac40d082e85397f100c3d8377b1f28811485def4) Reviewed-on: https://git-master.nvidia.com/r/1666445 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/fifo_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/fifo_gk20a.c14
1 files changed, 9 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index fea46a0e..e12576d2 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * GK20A Graphics FIFO (gr host) 2 * GK20A Graphics FIFO (gr host)
3 * 3 *
4 * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -1647,28 +1647,32 @@ static bool gk20a_fifo_handle_mmu_fault(
1647 * Disable the channel/TSG from hw and increment syncpoints. 1647 * Disable the channel/TSG from hw and increment syncpoints.
1648 */ 1648 */
1649 if (tsg) { 1649 if (tsg) {
1650 if (!g->fifo.deferred_reset_pending) { 1650 if (g->fifo.deferred_reset_pending) {
1651 gk20a_disable_tsg(tsg);
1652 } else {
1651 if (!fake_fault) 1653 if (!fake_fault)
1652 gk20a_fifo_set_ctx_mmu_error_tsg(g, 1654 gk20a_fifo_set_ctx_mmu_error_tsg(g,
1653 tsg); 1655 tsg);
1654 verbose = gk20a_fifo_error_tsg(g, tsg); 1656 verbose = gk20a_fifo_error_tsg(g, tsg);
1657 gk20a_fifo_abort_tsg(g, tsg->tsgid, false);
1655 } 1658 }
1656 gk20a_fifo_abort_tsg(g, tsg->tsgid, false);
1657 1659
1658 /* put back the ref taken early above */ 1660 /* put back the ref taken early above */
1659 if (refch) 1661 if (refch)
1660 gk20a_channel_put(ch); 1662 gk20a_channel_put(ch);
1661 } else if (ch) { 1663 } else if (ch) {
1662 if (refch) { 1664 if (refch) {
1663 if (!g->fifo.deferred_reset_pending) { 1665 if (g->fifo.deferred_reset_pending) {
1666 g->ops.fifo.disable_channel(ch);
1667 } else {
1664 if (!fake_fault) 1668 if (!fake_fault)
1665 gk20a_fifo_set_ctx_mmu_error_ch( 1669 gk20a_fifo_set_ctx_mmu_error_ch(
1666 g, refch); 1670 g, refch);
1667 1671
1668 verbose = gk20a_fifo_error_ch(g, 1672 verbose = gk20a_fifo_error_ch(g,
1669 refch); 1673 refch);
1674 gk20a_channel_abort(ch, false);
1670 } 1675 }
1671 gk20a_channel_abort(ch, false);
1672 gk20a_channel_put(ch); 1676 gk20a_channel_put(ch);
1673 } else { 1677 } else {
1674 nvgpu_err(g, 1678 nvgpu_err(g,