gpu: nvgpu: Set PB timeout only in gk20a

PB timeout has been removed in gm20b, so write it only in gk20a.

Change-Id: I2aab92fe7d1d5de151dad768f8b3f6901ec0bbb0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/486358
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>

1 files changed, 14 insertions, 5 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index b1cd50ea..4363129d 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -430,11 +430,8 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g)
                 gk20a_writel(g, pbdma_timeout_r(i), timeout);
         }
 
-        if (tegra_platform_is_silicon()) {
-                timeout = gk20a_readl(g, fifo_pb_timeout_r());
-                timeout &= ~fifo_pb_timeout_detection_enabled_f();
-                gk20a_writel(g, fifo_pb_timeout_r(), timeout);
-        }
+        if (g->ops.fifo.apply_pb_timeout)
+                g->ops.fifo.apply_pb_timeout(g);
 
         timeout = GRFIFO_TIMEOUT_CHECK_PERIOD_US |
                         fifo_eng_timeout_detection_enabled_f();
@@ -1949,8 +1946,20 @@ int gk20a_fifo_wait_engine_idle(struct gk20a *g)
         return ret;
 }
 
+static void gk20a_fifo_apply_pb_timeout(struct gk20a *g)
+{
+        u32 timeout;
+
+        if (tegra_platform_is_silicon()) {
+                timeout = gk20a_readl(g, fifo_pb_timeout_r());
+                timeout &= ~fifo_pb_timeout_detection_enabled_f();
+                gk20a_writel(g, fifo_pb_timeout_r(), timeout);
+        }
+}
+
 void gk20a_init_fifo(struct gpu_ops *gops)
 {
         gk20a_init_channel(gops);
         gops->fifo.trigger_mmu_fault = gk20a_fifo_trigger_mmu_fault;
+        gops->fifo.apply_pb_timeout = gk20a_fifo_apply_pb_timeout;
 }