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author | Seema Khowala <seemaj@nvidia.com> | 2017-02-28 12:58:10 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-03-02 18:05:28 -0500 |
commit | 0c155313e75a82a409d3438cc982ee30bb453d16 (patch) | |
tree | 5d4d059ca20c4fad04ecd7657080805aad6c5d0a /drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |
parent | ee93b209634a60d79fb4dbd05362b01b8d389603 (diff) |
gpu: nvgpu: use litter val for pbdma/eng *status__size*
fifo_pbdma_status__size_1_v() and fifo_engine_status__size_1_v()
are not same for all gpus. Use litter value to calculate chip
specific fifo*status__size_1(v)
JIRA GV11B-45
Change-Id: I3d3d45bf79d15e14739fcc18cb1ca987669d5c11
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1312688
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/fifo_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 0d3a75fc..95351a43 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -3115,9 +3115,11 @@ bool gk20a_fifo_mmu_fault_pending(struct gk20a *g) | |||
3115 | 3115 | ||
3116 | bool gk20a_fifo_is_engine_busy(struct gk20a *g) | 3116 | bool gk20a_fifo_is_engine_busy(struct gk20a *g) |
3117 | { | 3117 | { |
3118 | unsigned int i; | 3118 | u32 i, host_num_engines; |
3119 | |||
3120 | host_num_engines = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_ENGINES); | ||
3119 | 3121 | ||
3120 | for (i = 0; i < fifo_engine_status__size_1_v(); i++) { | 3122 | for (i = 0; i < host_num_engines; i++) { |
3121 | u32 status = gk20a_readl(g, fifo_engine_status_r(i)); | 3123 | u32 status = gk20a_readl(g, fifo_engine_status_r(i)); |
3122 | if (fifo_engine_status_engine_v(status) == | 3124 | if (fifo_engine_status_engine_v(status) == |
3123 | fifo_engine_status_engine_busy_v()) | 3125 | fifo_engine_status_engine_busy_v()) |
@@ -3131,14 +3133,17 @@ int gk20a_fifo_wait_engine_idle(struct gk20a *g) | |||
3131 | struct nvgpu_timeout timeout; | 3133 | struct nvgpu_timeout timeout; |
3132 | unsigned long delay = GR_IDLE_CHECK_DEFAULT; | 3134 | unsigned long delay = GR_IDLE_CHECK_DEFAULT; |
3133 | int ret = -ETIMEDOUT; | 3135 | int ret = -ETIMEDOUT; |
3134 | u32 i; | 3136 | u32 i, host_num_engines; |
3135 | 3137 | ||
3136 | gk20a_dbg_fn(""); | 3138 | gk20a_dbg_fn(""); |
3137 | 3139 | ||
3140 | host_num_engines = | ||
3141 | nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_ENGINES); | ||
3142 | |||
3138 | nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g), | 3143 | nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g), |
3139 | NVGPU_TIMER_CPU_TIMER); | 3144 | NVGPU_TIMER_CPU_TIMER); |
3140 | 3145 | ||
3141 | for (i = 0; i < fifo_engine_status__size_1_v(); i++) { | 3146 | for (i = 0; i < host_num_engines; i++) { |
3142 | do { | 3147 | do { |
3143 | u32 status = gk20a_readl(g, fifo_engine_status_r(i)); | 3148 | u32 status = gk20a_readl(g, fifo_engine_status_r(i)); |
3144 | if (!fifo_engine_status_engine_v(status)) { | 3149 | if (!fifo_engine_status_engine_v(status)) { |