gpu: nvgpu: switch gk20a nonstall ops to #defines

Fix MISRA rule 10.1 violations involving gk20a_nonstall_ops
enums by replacing them with with corresponding #defines.

Because these values can be used in expressions that require
unsigned values (e.g. bitwise OR) we cannot use enums.

The g->ce2.isr_nonstall() function was previously returning an
int that was a combination of gk20a_nonstall_ops enum bits which
led to the violations.

JIRA NVGPU-650

Change-Id: I6210aacec8829b3c8d339c5fe3db2f3069c67406
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1796242
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 2 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 4628de4f..20fb51e7 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -2720,7 +2720,7 @@ void gk20a_fifo_isr(struct gk20a *g)
         return;
 }
 
-enum gk20a_nonstall_ops gk20a_fifo_nonstall_isr(struct gk20a *g)
+u32 gk20a_fifo_nonstall_isr(struct gk20a *g)
 {
         u32 fifo_intr = gk20a_readl(g, fifo_intr_0_r());
         u32 clear_intr = 0;
@@ -2732,7 +2732,7 @@ enum gk20a_nonstall_ops gk20a_fifo_nonstall_isr(struct gk20a *g)
 
         gk20a_writel(g, fifo_intr_0_r(), clear_intr);
 
-        return gk20a_nonstall_ops_wakeup_semaphore;
+        return GK20A_NONSTALL_OPS_WAKEUP_SEMAPHORE;
 }
 
 void gk20a_fifo_issue_preempt(struct gk20a *g, u32 id, bool is_tsg)