diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-03-16 16:22:26 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-04-04 19:04:26 -0400 |
commit | 0778d7f33181e4f945083e8e051d5f9476fe5968 (patch) | |
tree | 5e181d064505776dc5f19205d83f0351214a501d /drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |
parent | 06fe28567d45c8fb1c2a04f0f007fa5d750b849d (diff) |
gpu: nvgpu: add teardown_ch_tsg fifo ops
teardown_ch_tsg fifo ops added as t19x s/w recovery procedure
is different than legacy chips.
JIRA GPUT19X-7
Change-Id: I5b88f2c1a19d309e5c97c588ddf9689163a75fea
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1327932
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/fifo_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 40 |
1 files changed, 29 insertions, 11 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 6a9a22b2..f7f39207 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -997,7 +997,7 @@ clean_up: | |||
997 | return err; | 997 | return err; |
998 | } | 998 | } |
999 | 999 | ||
1000 | static void gk20a_fifo_handle_runlist_event(struct gk20a *g) | 1000 | void gk20a_fifo_handle_runlist_event(struct gk20a *g) |
1001 | { | 1001 | { |
1002 | u32 runlist_event = gk20a_readl(g, fifo_intr_runlist_r()); | 1002 | u32 runlist_event = gk20a_readl(g, fifo_intr_runlist_r()); |
1003 | 1003 | ||
@@ -1276,7 +1276,7 @@ bool gk20a_is_fault_engine_subid_gpc(struct gk20a *g, u32 engine_subid) | |||
1276 | return (engine_subid == fifo_intr_mmu_fault_info_engine_subid_gpc_v()); | 1276 | return (engine_subid == fifo_intr_mmu_fault_info_engine_subid_gpc_v()); |
1277 | } | 1277 | } |
1278 | 1278 | ||
1279 | static bool gk20a_fifo_should_defer_engine_reset(struct gk20a *g, u32 engine_id, | 1279 | bool gk20a_fifo_should_defer_engine_reset(struct gk20a *g, u32 engine_id, |
1280 | u32 engine_subid, bool fake_fault) | 1280 | u32 engine_subid, bool fake_fault) |
1281 | { | 1281 | { |
1282 | u32 engine_enum = ENGINE_INVAL_GK20A; | 1282 | u32 engine_enum = ENGINE_INVAL_GK20A; |
@@ -1831,9 +1831,9 @@ void gk20a_fifo_recover_tsg(struct gk20a *g, u32 tsgid, bool verbose) | |||
1831 | nvgpu_mutex_release(&g->dbg_sessions_lock); | 1831 | nvgpu_mutex_release(&g->dbg_sessions_lock); |
1832 | } | 1832 | } |
1833 | 1833 | ||
1834 | void gk20a_fifo_recover(struct gk20a *g, u32 __engine_ids, | 1834 | void gk20a_fifo_teardown_ch_tsg(struct gk20a *g, u32 __engine_ids, |
1835 | u32 hw_id, bool id_is_tsg, | 1835 | u32 hw_id, unsigned int id_type, unsigned int rc_type, |
1836 | bool id_is_known, bool verbose) | 1836 | struct mmu_fault_info *mmfault) |
1837 | { | 1837 | { |
1838 | unsigned long engine_id, i; | 1838 | unsigned long engine_id, i; |
1839 | unsigned long _engine_ids = __engine_ids; | 1839 | unsigned long _engine_ids = __engine_ids; |
@@ -1843,12 +1843,8 @@ void gk20a_fifo_recover(struct gk20a *g, u32 __engine_ids, | |||
1843 | u32 ref_type; | 1843 | u32 ref_type; |
1844 | u32 ref_id; | 1844 | u32 ref_id; |
1845 | u32 ref_id_is_tsg = false; | 1845 | u32 ref_id_is_tsg = false; |
1846 | 1846 | bool id_is_known = (id_type != ID_TYPE_UNKNOWN) ? true : false; | |
1847 | if (verbose) | 1847 | bool id_is_tsg = (id_type == ID_TYPE_TSG) ? true : false; |
1848 | gk20a_debug_dump(g->dev); | ||
1849 | |||
1850 | if (g->ops.ltc.flush) | ||
1851 | g->ops.ltc.flush(g); | ||
1852 | 1848 | ||
1853 | if (id_is_known) { | 1849 | if (id_is_known) { |
1854 | engine_ids = gk20a_fifo_engines_on_id(g, hw_id, id_is_tsg); | 1850 | engine_ids = gk20a_fifo_engines_on_id(g, hw_id, id_is_tsg); |
@@ -1916,6 +1912,27 @@ void gk20a_fifo_recover(struct gk20a *g, u32 __engine_ids, | |||
1916 | } | 1912 | } |
1917 | } | 1913 | } |
1918 | 1914 | ||
1915 | void gk20a_fifo_recover(struct gk20a *g, u32 __engine_ids, | ||
1916 | u32 hw_id, bool id_is_tsg, | ||
1917 | bool id_is_known, bool verbose) | ||
1918 | { | ||
1919 | unsigned int id_type; | ||
1920 | |||
1921 | if (verbose) | ||
1922 | gk20a_debug_dump(g->dev); | ||
1923 | |||
1924 | if (g->ops.ltc.flush) | ||
1925 | g->ops.ltc.flush(g); | ||
1926 | |||
1927 | if (id_is_known) | ||
1928 | id_type = id_is_tsg ? ID_TYPE_TSG : ID_TYPE_CHANNEL; | ||
1929 | else | ||
1930 | id_type = ID_TYPE_UNKNOWN; | ||
1931 | |||
1932 | g->ops.fifo.teardown_ch_tsg(g, __engine_ids, hw_id, id_type, | ||
1933 | RC_TYPE_NORMAL, NULL); | ||
1934 | } | ||
1935 | |||
1919 | /* force reset channel and tsg (if it's part of one) */ | 1936 | /* force reset channel and tsg (if it's part of one) */ |
1920 | int gk20a_fifo_force_reset_ch(struct channel_gk20a *ch, | 1937 | int gk20a_fifo_force_reset_ch(struct channel_gk20a *ch, |
1921 | u32 err_code, bool verbose) | 1938 | u32 err_code, bool verbose) |
@@ -4225,4 +4242,5 @@ void gk20a_init_fifo(struct gpu_ops *gops) | |||
4225 | gops->fifo.userd_gp_get = gk20a_fifo_userd_gp_get; | 4242 | gops->fifo.userd_gp_get = gk20a_fifo_userd_gp_get; |
4226 | gops->fifo.userd_gp_put = gk20a_fifo_userd_gp_put; | 4243 | gops->fifo.userd_gp_put = gk20a_fifo_userd_gp_put; |
4227 | gops->fifo.pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val; | 4244 | gops->fifo.pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val; |
4245 | gops->fifo.teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg; | ||
4228 | } | 4246 | } |