gpu: nvgpu: Move all FB programming to FB HAL

Move all programming of FB to fb_*.c files, and remove the inclusion
of FB hardware headers from other files.

TLB invalidate function took previously a pointer to VM, but the new
API takes only a PDB mem_desc, because FB does not need to know about
higher level VM.

GPC MMU is programmed from the same function as FB MMU, so added
dependency to GR hardware header to FB.

GP106 ACR was also triggering a VPR fetch, but that's not applicable
to dGPU, so removed that call.

Change-Id: I4eb69377ac3745da205907626cf60948b7c5392a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1321516
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 101 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/fb_gk20a.c b/drivers/gpu/nvgpu/gk20a/fb_gk20a.c
index 1efa56fb..4b8baad5 100644
--- a/drivers/gpu/nvgpu/gk20a/fb_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fb_gk20a.c
@@ -14,6 +14,8 @@
  */
 
 #include <linux/types.h>
+#include <trace/events/gk20a.h>
+#include <linux/delay.h>
 
 #include "gk20a.h"
 #include "kind_gk20a.h"
@@ -40,6 +42,13 @@ void fb_gk20a_reset(struct gk20a *g)
         gk20a_writel(g, mc_elpg_enable_r(), val);
 }
 
+void gk20a_fb_init_hw(struct gk20a *g)
+{
+        gk20a_writel(g, fb_niso_flush_sysmem_addr_r(),
+                     g->ops.mm.get_iova_addr(g, g->mm.sysmem_flush.sgt->sgl, 0)
+                     >> 8);
+}
+
 static void gk20a_fb_set_mmu_page_size(struct gk20a *g)
 {
         /* set large page size in fb */
@@ -62,12 +71,104 @@ static unsigned int gk20a_fb_compressible_page_size(struct gk20a *g)
         return SZ_64K;
 }
 
+bool gk20a_fb_debug_mode_enabled(struct gk20a *g)
+{
+        u32 debug_ctrl = gk20a_readl(g, fb_mmu_debug_ctrl_r());
+        return fb_mmu_debug_ctrl_debug_v(debug_ctrl) ==
+                fb_mmu_debug_ctrl_debug_enabled_v();
+}
+
+static void gk20a_fb_set_debug_mode(struct gk20a *g, bool enable)
+{
+        u32 reg_val, debug_ctrl;
+
+        reg_val = gk20a_readl(g, fb_mmu_debug_ctrl_r());
+        if (enable) {
+                debug_ctrl = fb_mmu_debug_ctrl_debug_enabled_f();
+                g->mmu_debug_ctrl = true;
+        } else {
+                debug_ctrl = fb_mmu_debug_ctrl_debug_disabled_f();
+                g->mmu_debug_ctrl = false;
+        }
+
+        reg_val = set_field(reg_val,
+                                fb_mmu_debug_ctrl_debug_m(), debug_ctrl);
+        gk20a_writel(g, fb_mmu_debug_ctrl_r(), reg_val);
+}
+
+void gk20a_fb_tlb_invalidate(struct gk20a *g, struct mem_desc *pdb)
+{
+        struct nvgpu_timeout timeout;
+        u32 addr_lo;
+        u32 data;
+
+        gk20a_dbg_fn("");
+
+        /* pagetables are considered sw states which are preserved after
+           prepare_poweroff. When gk20a deinit releases those pagetables,
+           common code in vm unmap path calls tlb invalidate that touches
+           hw. Use the power_on flag to skip tlb invalidation when gpu
+           power is turned off */
+
+        if (!g->power_on)
+                return;
+
+        addr_lo = u64_lo32(gk20a_mem_get_base_addr(g, pdb, 0) >> 12);
+
+        nvgpu_mutex_acquire(&g->mm.tlb_lock);
+
+        trace_gk20a_mm_tlb_invalidate(dev_name(g->dev));
+
+        nvgpu_timeout_init(g, &timeout, 1000, NVGPU_TIMER_RETRY_TIMER);
+
+        do {
+                data = gk20a_readl(g, fb_mmu_ctrl_r());
+                if (fb_mmu_ctrl_pri_fifo_space_v(data) != 0)
+                        break;
+                udelay(2);
+        } while (!nvgpu_timeout_expired_msg(&timeout,
+                                         "wait mmu fifo space"));
+
+        if (nvgpu_timeout_peek_expired(&timeout))
+                goto out;
+
+        nvgpu_timeout_init(g, &timeout, 1000, NVGPU_TIMER_RETRY_TIMER);
+
+        gk20a_writel(g, fb_mmu_invalidate_pdb_r(),
+                fb_mmu_invalidate_pdb_addr_f(addr_lo) |
+                gk20a_aperture_mask(g, pdb,
+                  fb_mmu_invalidate_pdb_aperture_sys_mem_f(),
+                  fb_mmu_invalidate_pdb_aperture_vid_mem_f()));
+
+        gk20a_writel(g, fb_mmu_invalidate_r(),
+                fb_mmu_invalidate_all_va_true_f() |
+                fb_mmu_invalidate_trigger_true_f());
+
+        do {
+                data = gk20a_readl(g, fb_mmu_ctrl_r());
+                if (fb_mmu_ctrl_pri_fifo_empty_v(data) !=
+                        fb_mmu_ctrl_pri_fifo_empty_false_f())
+                        break;
+                udelay(2);
+        } while (!nvgpu_timeout_expired_msg(&timeout,
+                                         "wait mmu invalidate"));
+
+        trace_gk20a_mm_tlb_invalidate_done(dev_name(g->dev));
+
+out:
+        nvgpu_mutex_release(&g->mm.tlb_lock);
+}
+
 void gk20a_init_fb(struct gpu_ops *gops)
 {
+        gops->fb.init_hw = gk20a_fb_init_hw;
         gops->fb.reset = fb_gk20a_reset;
         gops->fb.set_mmu_page_size = gk20a_fb_set_mmu_page_size;
         gops->fb.compression_page_size = gk20a_fb_compression_page_size;
         gops->fb.compressible_page_size = gk20a_fb_compressible_page_size;
+        gops->fb.is_debug_mode_enabled = gk20a_fb_debug_mode_enabled;
+        gops->fb.set_debug_mode = gk20a_fb_set_debug_mode;
+        gops->fb.tlb_invalidate = gk20a_fb_tlb_invalidate;
         gk20a_init_uncompressed_kind_map();
         gk20a_init_kind_attr();
 }