gpu: nvgpu: Reset streaming on perfbuf_enable and perfbuf_disable

Similarly to css_hw_(enable|disable)_snapshot the HWPM
state should be reset on perfbuf_enable and perfbuf_disable
to avoid leaking snapshot data into a freshly mapped buffer.

Bug 1960846

Change-Id: I94826b209ef4b8cb6ad44d3b8667745270c6a7e1
Signed-off-by: Martin Radev <mradev@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1676009
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 25 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
index fd31ab89..5d428afa 100644
--- a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
@@ -36,6 +36,27 @@
 #include <nvgpu/hw/gk20a/hw_therm_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_gr_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_perf_gk20a.h>
+#include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
+
+static void gk20a_perfbuf_reset_streaming(struct gk20a *g)
+{
+        u32 engine_status;
+        u32 num_unread_bytes;
+
+        g->ops.mc.reset(g, mc_enable_perfmon_enabled_f());
+
+        engine_status = gk20a_readl(g, perf_pmasys_enginestatus_r());
+        WARN_ON(0u ==
+                (engine_status & perf_pmasys_enginestatus_rbufempty_empty_f()));
+
+        gk20a_writel(g, perf_pmasys_control_r(),
+                perf_pmasys_control_membuf_clear_status_doit_f());
+
+        num_unread_bytes = gk20a_readl(g, perf_pmasys_mem_bytes_r());
+        if (num_unread_bytes != 0u) {
+                gk20a_writel(g, perf_pmasys_mem_bump_r(), num_unread_bytes);
+        }
+}
 
 /*
  * API to get first channel from the list of all channels
@@ -316,6 +337,8 @@ int gk20a_perfbuf_enable_locked(struct gk20a *g, u64 offset, u32 size)
 
         g->ops.mm.init_inst_block(&mm->perfbuf.inst_block, mm->perfbuf.vm, 0);
 
+        gk20a_perfbuf_reset_streaming(g);
+
         virt_addr_lo = u64_lo32(offset);
         virt_addr_hi = u64_hi32(offset);
 
@@ -349,6 +372,8 @@ int gk20a_perfbuf_disable_locked(struct gk20a *g)
                 return err;
         }
 
+        gk20a_perfbuf_reset_streaming(g);
+
         gk20a_writel(g, perf_pmasys_outbase_r(), 0);
         gk20a_writel(g, perf_pmasys_outbaseupper_r(),
                         perf_pmasys_outbaseupper_ptr_f(0));