diff options
author | sujeet baranwal <sbaranwal@nvidia.com> | 2015-02-19 13:34:51 -0500 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-04-04 21:08:16 -0400 |
commit | 8d1ab756ed8a7f4d3138dc5da9d2de9f52915261 (patch) | |
tree | 969a5a5aead991570d8c8c56acd41adb2103b8f5 /drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c | |
parent | ac205be1d31b00c5641df81d53f2da5f143d3354 (diff) |
gpu: nvgpu: ioctl for flushing GPU L2
CUDA devtools need to be able to flush the GPU's cache
in a sideband fashion and so cannot use methods. This
change implements an nvgpu_gpu_ioctl to flush and
optionally invalidate the GPU's L2 cache and flush fb.
Change-Id: Ib06a0bc8d8880ffbfe4b056518cc3c3df0cc4988
Signed-off-by: sujeet baranwal <sbaranwal@nvidia.com>
Signed-off-by: Mayank Kaushik <mkaushik@nvidia.com>
Reviewed-on: http://git-master/r/671809
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c index 5bee34fc..ffb52549 100644 --- a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c | |||
@@ -412,19 +412,16 @@ long gk20a_dbg_gpu_dev_ioctl(struct file *filp, unsigned int cmd, | |||
412 | case NVGPU_DBG_GPU_IOCTL_BIND_CHANNEL: | 412 | case NVGPU_DBG_GPU_IOCTL_BIND_CHANNEL: |
413 | err = dbg_bind_channel_gk20a(dbg_s, | 413 | err = dbg_bind_channel_gk20a(dbg_s, |
414 | (struct nvgpu_dbg_gpu_bind_channel_args *)buf); | 414 | (struct nvgpu_dbg_gpu_bind_channel_args *)buf); |
415 | gk20a_dbg(gpu_dbg_gpu_dbg, "ret=%d", err); | ||
416 | break; | 415 | break; |
417 | 416 | ||
418 | case NVGPU_DBG_GPU_IOCTL_REG_OPS: | 417 | case NVGPU_DBG_GPU_IOCTL_REG_OPS: |
419 | err = nvgpu_ioctl_channel_reg_ops(dbg_s, | 418 | err = nvgpu_ioctl_channel_reg_ops(dbg_s, |
420 | (struct nvgpu_dbg_gpu_exec_reg_ops_args *)buf); | 419 | (struct nvgpu_dbg_gpu_exec_reg_ops_args *)buf); |
421 | gk20a_dbg(gpu_dbg_gpu_dbg, "ret=%d", err); | ||
422 | break; | 420 | break; |
423 | 421 | ||
424 | case NVGPU_DBG_GPU_IOCTL_POWERGATE: | 422 | case NVGPU_DBG_GPU_IOCTL_POWERGATE: |
425 | err = nvgpu_ioctl_powergate_gk20a(dbg_s, | 423 | err = nvgpu_ioctl_powergate_gk20a(dbg_s, |
426 | (struct nvgpu_dbg_gpu_powergate_args *)buf); | 424 | (struct nvgpu_dbg_gpu_powergate_args *)buf); |
427 | gk20a_dbg(gpu_dbg_gpu_dbg, "ret=%d", err); | ||
428 | break; | 425 | break; |
429 | 426 | ||
430 | case NVGPU_DBG_GPU_IOCTL_EVENTS_CTRL: | 427 | case NVGPU_DBG_GPU_IOCTL_EVENTS_CTRL: |
@@ -460,6 +457,8 @@ long gk20a_dbg_gpu_dev_ioctl(struct file *filp, unsigned int cmd, | |||
460 | break; | 457 | break; |
461 | } | 458 | } |
462 | 459 | ||
460 | gk20a_dbg(gpu_dbg_gpu_dbg, "ret=%d", err); | ||
461 | |||
463 | if ((err == 0) && (_IOC_DIR(cmd) & _IOC_READ)) | 462 | if ((err == 0) && (_IOC_DIR(cmd) & _IOC_READ)) |
464 | err = copy_to_user((void __user *)arg, | 463 | err = copy_to_user((void __user *)arg, |
465 | buf, _IOC_SIZE(cmd)); | 464 | buf, _IOC_SIZE(cmd)); |
@@ -741,6 +740,8 @@ static int nvgpu_dbg_gpu_ioctl_suspend_resume_sm( | |||
741 | bool ch_is_curr_ctx; | 740 | bool ch_is_curr_ctx; |
742 | int err = 0, action = args->mode; | 741 | int err = 0, action = args->mode; |
743 | 742 | ||
743 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "action: %d", args->mode); | ||
744 | |||
744 | mutex_lock(&g->dbg_sessions_lock); | 745 | mutex_lock(&g->dbg_sessions_lock); |
745 | 746 | ||
746 | /* Suspend GPU context switching */ | 747 | /* Suspend GPU context switching */ |