gpu: nvgpu: create a hal function for smpc war

Create a HAL function for applying the SMPC workaround.The workaround
is only needed on gk20a, and not on gm20b.

Change-Id: I9edc741df32ab7d1dad38ecc56f238828128bfef
Signed-off-by: Mayank Kaushik <mkaushik@nvidia.com>
Reviewed-on: http://git-master/r/539187
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 1 insertions, 32 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
index 6af54e68..94486064 100644
--- a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
@@ -686,39 +686,8 @@ static int nvgpu_dbg_gpu_ioctl_smpc_ctxsw_mode(struct dbg_session_gk20a *dbg_s,
                           "error (%d) during smpc ctxsw mode update\n", err);
                 goto clean_up;
         }
-        /* The following regops are a hack/war to make up for the fact that we
-         * just scribbled into the ctxsw image w/o really knowing whether
-         * it was already swapped out in/out once or not, etc.
-         */
-        {
-                struct nvgpu_dbg_gpu_reg_op ops[4];
-                int i;
-                for (i = 0; i < ARRAY_SIZE(ops); i++) {
-                        ops[i].op     = NVGPU_DBG_GPU_REG_OP_WRITE_32;
-                        ops[i].type   = NVGPU_DBG_GPU_REG_OP_TYPE_GR_CTX;
-                        ops[i].status = NVGPU_DBG_GPU_REG_OP_STATUS_SUCCESS;
-                        ops[i].value_hi      = 0;
-                        ops[i].and_n_mask_lo = 0;
-                        ops[i].and_n_mask_hi = 0;
-                }
-                /* gr_pri_gpcs_tpcs_sm_dsm_perf_counter_control_sel1_r();*/
-                ops[0].offset   = 0x00419e08;
-                ops[0].value_lo = 0x1d;
-
-                /* gr_pri_gpcs_tpcs_sm_dsm_perf_counter_control5_r(); */
-                ops[1].offset   = 0x00419e58;
-                ops[1].value_lo = 0x1;
 
-                /* gr_pri_gpcs_tpcs_sm_dsm_perf_counter_control3_r(); */
-                ops[2].offset   = 0x00419e68;
-                ops[2].value_lo = 0xaaaa;
-
-                /* gr_pri_gpcs_tpcs_sm_dsm_perf_counter4_control_r(); */
-                ops[3].offset   = 0x00419f40;
-                ops[3].value_lo = 0x18;
-
-                err = dbg_s->ops->exec_reg_ops(dbg_s, ops, ARRAY_SIZE(ops));
-        }
+        err = g->ops.regops.apply_smpc_war(dbg_s);
 
  clean_up:
         mutex_unlock(&g->dbg_sessions_lock);