gpu: nvgpu: Combine delays with GK20A parameters

Specified locking timeout and IDDQ exit delay as GK20A PLL parameters,
and used this data instead of hard-coded numbers.

Change-Id: I59e16ed11fdba6911f2751195d182e68aed96851
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/735481
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

1 files changed, 0 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/clk_gk20a.h b/drivers/gpu/nvgpu/gk20a/clk_gk20a.h
index 9f5ea39e..8408f460 100644
--- a/drivers/gpu/nvgpu/gk20a/clk_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/clk_gk20a.h
@@ -79,7 +79,6 @@ struct clk_gk20a {
         struct clk *tegra_clk;
         struct pll gpc_pll;
         struct pll gpc_pll_last;
-        u32 pll_delay; /* default PLL settle time */
         struct mutex clk_mutex;
         bool sw_ready;
         bool clk_hw_on;