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authorAlex Frid <afrid@nvidia.com>2014-07-14 20:01:31 -0400
committerDan Willemsen <dwillemsen@nvidia.com>2015-03-18 15:10:29 -0400
commit3058fb2b960cf1da53fd25c5c8d286d60560615e (patch)
tree6a0b48f79161ed6c272948e6d4834bf7d83976ad /drivers/gpu/nvgpu/gk20a/clk_gk20a.h
parent5ea7ab10ecddc6d6f8d9c72ea6e60ba260389c63 (diff)
gpu: nvgpu: Use 1kHz resolution for GPCPLL programming
Used 1kHz resolution (instead of 1 MHz) for GPCPLL programming: limits specifications, calculating GPCPLL settings, storing target frequency values, and proving output from debug monitor. Updated comments in clock header to properly reflect frequency units. Bug 1450787 Change-Id: Ica58f794b82522288f2883c40626d82dbd794902 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/437943 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/clk_gk20a.h')
-rw-r--r--drivers/gpu/nvgpu/gk20a/clk_gk20a.h20
1 files changed, 10 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/clk_gk20a.h b/drivers/gpu/nvgpu/gk20a/clk_gk20a.h
index d2665259..533e6d1e 100644
--- a/drivers/gpu/nvgpu/gk20a/clk_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/clk_gk20a.h
@@ -31,18 +31,18 @@ enum {
31 31
32struct pll { 32struct pll {
33 u32 id; 33 u32 id;
34 u32 clk_in; /* MHz */ 34 u32 clk_in; /* KHz */
35 u32 M; 35 u32 M;
36 u32 N; 36 u32 N;
37 u32 PL; 37 u32 PL;
38 u32 freq; /* MHz */ 38 u32 freq; /* KHz */
39 bool enabled; 39 bool enabled;
40}; 40};
41 41
42struct pll_parms { 42struct pll_parms {
43 u32 min_freq, max_freq; /* MHz */ 43 u32 min_freq, max_freq; /* KHz */
44 u32 min_vco, max_vco; /* MHz */ 44 u32 min_vco, max_vco; /* KHz */
45 u32 min_u, max_u; /* MHz */ 45 u32 min_u, max_u; /* KHz */
46 u32 min_M, max_M; 46 u32 min_M, max_M;
47 u32 min_N, max_N; 47 u32 min_N, max_N;
48 u32 min_PL, max_PL; 48 u32 min_PL, max_PL;
@@ -60,7 +60,7 @@ struct clk_gk20a {
60 60
61struct gpufreq_table_data { 61struct gpufreq_table_data {
62 unsigned int index; 62 unsigned int index;
63 unsigned int frequency; /* MHz */ 63 unsigned int frequency; /* Hz */
64}; 64};
65 65
66struct gpufreq_table_data *tegra_gpufreq_table_get(void); 66struct gpufreq_table_data *tegra_gpufreq_table_get(void);
@@ -82,13 +82,13 @@ extern struct pll_parms gpc_pll_params;
82 82
83static inline unsigned long rate_gpc2clk_to_gpu(unsigned long rate) 83static inline unsigned long rate_gpc2clk_to_gpu(unsigned long rate)
84{ 84{
85 /* convert the MHz gpc2clk frequency to Hz gpcpll frequency */ 85 /* convert the kHz gpc2clk frequency to Hz gpcpll frequency */
86 return (rate * MHZ) / 2; 86 return (rate * KHZ) / 2;
87} 87}
88static inline unsigned long rate_gpu_to_gpc2clk(unsigned long rate) 88static inline unsigned long rate_gpu_to_gpc2clk(unsigned long rate)
89{ 89{
90 /* convert the Hz gpcpll frequency to MHz gpc2clk frequency */ 90 /* convert the Hz gpcpll frequency to kHz gpc2clk frequency */
91 return (rate * 2) / MHZ; 91 return (rate * 2) / KHZ;
92} 92}
93 93
94#endif /* _NVHOST_CLK_GK20A_H_ */ 94#endif /* _NVHOST_CLK_GK20A_H_ */