gpu: nvgpu: Change GPCPLL rev C1 control settings

Updated DFS control settings for GPCPLL revision C1 per characterization
data.

Bug 1942222

Change-Id: Iab5147e13ef70df980d36589328abafd8f5495b8
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/1502741
(cherry picked from commit 5ea62c9e264de86f6e5a40a7f31054ab31b3196f)
Reviewed-on: https://git-master.nvidia.com/r/1525830
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

1 files changed, 2 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/clk_gk20a.h b/drivers/gpu/nvgpu/gk20a/clk_gk20a.h
index e8c14e43..23e57ed4 100644
--- a/drivers/gpu/nvgpu/gk20a/clk_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/clk_gk20a.h
@@ -77,6 +77,8 @@ struct pll_parms {
         u32 lock_timeout;
         u32 na_lock_delay;
         u32 iddq_exit_delay;
+        /* NA mode DFS control */
+        u32 dfs_ctrl;
 };
 
 struct namemap_cfg;