gpu: nvgpu: gm20b expose gpcclk through CCF

Register gpcclk with Common Clock Framework to expose GPCPLL frequency
control

Bug 200233943

Change-Id: Id6f7bbaca15f22157b91b092c2a035af933fa71e
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-on: http://git-master/r/1236979
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 8 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/clk_gk20a.h b/drivers/gpu/nvgpu/gk20a/clk_gk20a.h
index aefbc5d5..43583f2e 100644
--- a/drivers/gpu/nvgpu/gk20a/clk_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/clk_gk20a.h
@@ -17,6 +17,7 @@
 #define CLK_GK20A_H
 
 #include <linux/mutex.h>
+#include <linux/clk-provider.h>
 
 #define GPUFREQ_TABLE_END     ~(u32)1
 enum {
@@ -79,6 +80,9 @@ struct namemap_cfg;
 struct clk_gk20a {
         struct gk20a *g;
         struct clk *tegra_clk;
+#if defined(CONFIG_COMMON_CLK)
+        struct clk_hw hw;
+#endif
         struct pll gpc_pll;
         struct pll gpc_pll_last;
         struct mutex clk_mutex;
@@ -89,6 +93,10 @@ struct clk_gk20a {
         bool debugfs_set;
 };
 
+#if defined(CONFIG_COMMON_CLK)
+#define to_clk_gk20a(_hw) container_of(_hw, struct clk_gk20a, hw)
+#endif
+
 struct gpu_ops;
 #ifdef CONFIG_TEGRA_CLK_FRAMEWORK
 void gk20a_init_clk_ops(struct gpu_ops *gops);