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authorDebarshi Dutta <ddutta@nvidia.com>2018-09-04 08:09:36 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-09-18 02:39:24 -0400
commit2517d59be282426eec7a97745b76d745ff36c388 (patch)
treefaf915b5cfffb781918d674ec7d769feb7e98ac8 /drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.h
parent8381eeea4f9b4717854387068ddf9244973e7d0d (diff)
gpu: nvgpu: move channel_sync_gk20a.* to common directory
1) Move channel_sync_gk20a.* from gk20a/ to common/ directory as they donot program any hardware registers. Also as an add-on rename channel_sync_gk20a.* to channel_sync.* and update the headers in required files. 2) Rename the struct gk20a_channel_sync to struct nvgpu_channel_sync. Also, corresponding syncpt and semaphore versions of the struct alongwith related methods are renamed by removing "gk20a" from their names and adding "nvgpu". 3) Add misra-c cleanups Jira NVGPU-1086 Change-Id: I4e0e21803ca3858dd7a5fc4d2454dba1f1bfcecd Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1812594 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.h')
-rw-r--r--drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.h112
1 files changed, 0 insertions, 112 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.h b/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.h
deleted file mode 100644
index e0e318d2..00000000
--- a/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.h
+++ /dev/null
@@ -1,112 +0,0 @@
1/*
2 * drivers/video/tegra/host/gk20a/channel_sync_gk20a.h
3 *
4 * GK20A Channel Synchronization Abstraction
5 *
6 * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 */
26
27#ifndef NVGPU_GK20A_CHANNEL_SYNC_GK20A_H
28#define NVGPU_GK20A_CHANNEL_SYNC_GK20A_H
29
30struct gk20a_channel_sync;
31struct priv_cmd_entry;
32struct channel_gk20a;
33struct gk20a_fence;
34struct gk20a;
35struct nvgpu_semaphore;
36
37struct gk20a_channel_sync {
38 nvgpu_atomic_t refcount;
39
40 /* Generate a gpu wait cmdbuf from syncpoint.
41 * Returns a gpu cmdbuf that performs the wait when executed
42 */
43 int (*wait_syncpt)(struct gk20a_channel_sync *s, u32 id, u32 thresh,
44 struct priv_cmd_entry *entry);
45
46 /* Generate a gpu wait cmdbuf from sync fd.
47 * Returns a gpu cmdbuf that performs the wait when executed
48 */
49 int (*wait_fd)(struct gk20a_channel_sync *s, int fd,
50 struct priv_cmd_entry *entry, int max_wait_cmds);
51
52 /* Increment syncpoint/semaphore.
53 * Returns
54 * - a gpu cmdbuf that performs the increment when executed,
55 * - a fence that can be passed to wait_cpu() and is_expired().
56 */
57 int (*incr)(struct gk20a_channel_sync *s,
58 struct priv_cmd_entry *entry,
59 struct gk20a_fence *fence,
60 bool need_sync_fence,
61 bool register_irq);
62
63 /* Increment syncpoint/semaphore, so that the returned fence represents
64 * work completion (may need wfi) and can be returned to user space.
65 * Returns
66 * - a gpu cmdbuf that performs the increment when executed,
67 * - a fence that can be passed to wait_cpu() and is_expired(),
68 * - a gk20a_fence that signals when the incr has happened.
69 */
70 int (*incr_user)(struct gk20a_channel_sync *s,
71 int wait_fence_fd,
72 struct priv_cmd_entry *entry,
73 struct gk20a_fence *fence,
74 bool wfi,
75 bool need_sync_fence,
76 bool register_irq);
77
78 /* Reset the channel syncpoint/semaphore. */
79 void (*set_min_eq_max)(struct gk20a_channel_sync *s);
80
81 /*
82 * Set the channel syncpoint/semaphore to safe state
83 * This should be used to reset User managed syncpoint since we don't
84 * track threshold values for those syncpoints
85 */
86 void (*set_safe_state)(struct gk20a_channel_sync *s);
87
88 /* Returns the sync point id or negative number if no syncpt*/
89 int (*syncpt_id)(struct gk20a_channel_sync *s);
90
91 /* Returns the sync point address of sync point or 0 if not supported */
92 u64 (*syncpt_address)(struct gk20a_channel_sync *s);
93
94 /* Free the resources allocated by gk20a_channel_sync_create. */
95 void (*destroy)(struct gk20a_channel_sync *s);
96};
97
98void gk20a_channel_gen_sema_wait_cmd(struct channel_gk20a *c,
99 struct nvgpu_semaphore *sema, struct priv_cmd_entry *wait_cmd,
100 u32 wait_cmd_size, int pos);
101
102int gk20a_channel_gen_syncpt_wait_cmd(struct channel_gk20a *c,
103 u32 id, u32 thresh, struct priv_cmd_entry *wait_cmd,
104 u32 wait_cmd_size, int pos, bool preallocated);
105
106void gk20a_channel_sync_destroy(struct gk20a_channel_sync *sync,
107 bool set_safe_state);
108struct gk20a_channel_sync *gk20a_channel_sync_create(struct channel_gk20a *c,
109 bool user_managed);
110bool gk20a_channel_sync_needs_sync_framework(struct gk20a *g);
111
112#endif /* NVGPU_GK20A_CHANNEL_SYNC_GK20A_H */