gpu: nvgpu: decouple sema and hw sema

struct nvgpu_semaphore represents (mainly) a threshold value that a sema
at some index will get and struct nvgpu_semaphore_int (aka "hw_sema")
represents the allocation (and write access) of a semaphore index and
the next value that the sema at that index can have. The threshold
object doesn't need a pointer to the sema allocation that is not even
guaranteed to exist for the whole threshold lifetime, so replace the
pointer by the position of the sema in the sema pool.

This requires some modifications to pass a hw sema around explicitly
because it now represents write access more explicitly.

Delete also the index field of semaphore_int because it can be directly
derived from the offset in the sema location and is thus unnecessary.

Jira NVGPU-512

Change-Id: I40be523fd68327e2f9928f10de4f771fe24d49ee
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1658102
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 11 insertions, 10 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c
index 45d9ae9c..4b1be8b9 100644
--- a/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c
@@ -494,7 +494,7 @@ static void gk20a_channel_semaphore_launcher(
                   "wait completed (%d) for fence %p '%s', triggering gpu work",
                   err, fence, fence->name);
         sync_fence_put(fence);
-        nvgpu_semaphore_release(w->sema);
+        nvgpu_semaphore_release(w->sema, w->ch->hw_sema);
         nvgpu_semaphore_put(w->sema);
         nvgpu_kfree(g, w);
 }
@@ -522,7 +522,7 @@ static void add_sema_cmd(struct gk20a *g, struct channel_gk20a *c,
          * incr the underlying sema next_value.
          */
         if (!acquire)
-                nvgpu_semaphore_incr(s);
+                nvgpu_semaphore_incr(s, c->hw_sema);
 
         /* semaphore_a */
         nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010004);
@@ -561,17 +561,18 @@ static void add_sema_cmd(struct gk20a *g, struct channel_gk20a *c,
         }
 
         if (acquire)
-                gpu_sema_verbose_dbg(g, "(A) c=%d ACQ_GE %-4u owner=%-3d"
+                gpu_sema_verbose_dbg(g, "(A) c=%d ACQ_GE %-4u pool=%-3d"
                                      "va=0x%llx cmd_mem=0x%llx b=0x%llx off=%u",
                                      ch, nvgpu_semaphore_get_value(s),
-                                     s->hw_sema->ch->chid, va, cmd->gva,
+                                     s->location.pool->page_idx, va, cmd->gva,
                                      cmd->mem->gpu_va, ob);
         else
-                gpu_sema_verbose_dbg(g, "(R) c=%d INCR %u (%u) va=0x%llx "
-                                     "cmd_mem=0x%llx b=0x%llx off=%u",
+                gpu_sema_verbose_dbg(g, "(R) c=%d INCR %u (%u) pool=%-3d"
+                                     "va=0x%llx cmd_mem=0x%llx b=0x%llx off=%u",
                                      ch, nvgpu_semaphore_get_value(s),
-                                     nvgpu_semaphore_read(s), va, cmd->gva,
-                                     cmd->mem->gpu_va, ob);
+                                     nvgpu_semaphore_read(s),
+                                     s->location.pool->page_idx,
+                                     va, cmd->gva, cmd->mem->gpu_va, ob);
 }
 
 static int gk20a_channel_semaphore_wait_syncpt(
@@ -714,7 +715,7 @@ static int gk20a_channel_semaphore_wait_fd(
 
         /* worker takes one reference */
         nvgpu_semaphore_get(w->sema);
-        nvgpu_semaphore_incr(w->sema);
+        nvgpu_semaphore_incr(w->sema, c->hw_sema);
 
         /* GPU unblocked when the semaphore value increments. */
         add_sema_cmd(c->g, c, w->sema, wait_cmd, 8, true, false);
@@ -740,7 +741,7 @@ static int gk20a_channel_semaphore_wait_fd(
          */
         if (ret == 1) {
                 sync_fence_put(sync_fence);
-                nvgpu_semaphore_release(w->sema);
+                nvgpu_semaphore_release(w->sema, c->hw_sema);
                 nvgpu_semaphore_put(w->sema);
         }