gpu: nvgpu: Make graphics context property of TSG

Move graphics context ownership to TSG instead of channel. Combine
channel_ctx_gk20a and gr_ctx_desc to one structure, because the split
between them was arbitrary. Move context header to be property of
channel.

Bug 1842197

Change-Id: I410e3262f80b318d8528bcbec270b63a2d8d2ff9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1639532
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 2 insertions, 21 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h
index c13b1c58..29fa302f 100644
--- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h
@@ -31,7 +31,6 @@
 #include <nvgpu/atomic.h>
 
 struct gk20a;
-struct gr_gk20a;
 struct dbg_session_gk20a;
 struct gk20a_fence;
 struct fifo_profile_gk20a;
@@ -50,10 +49,6 @@ struct fifo_profile_gk20a;
 #define NVGPU_GPFIFO_FLAGS_SUPPORT_DETERMINISTIC        (1 << 1)
 #define NVGPU_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE     (1 << 2)
 
-/* Flags to be passed to g->ops.gr.alloc_obj_ctx() */
-#define NVGPU_OBJ_CTX_FLAGS_SUPPORT_GFXP                (1 << 1)
-#define NVGPU_OBJ_CTX_FLAGS_SUPPORT_CILP                (1 << 2)
-
 struct notification {
         struct {
                 u32 nanoseconds[2];
@@ -63,19 +58,6 @@ struct notification {
         u16 status;
 };
 
-/* contexts associated with a channel */
-struct channel_ctx_gk20a {
-        struct gr_ctx_desc      *gr_ctx;
-        struct patch_desc       patch_ctx;
-        struct zcull_ctx_desc   zcull_ctx;
-        struct pm_ctx_desc      pm_ctx;
-        u64     global_ctx_buffer_va[NR_GLOBAL_CTX_BUF_VA];
-        u64     global_ctx_buffer_size[NR_GLOBAL_CTX_BUF_VA];
-        int     global_ctx_buffer_index[NR_GLOBAL_CTX_BUF_VA];
-        bool    global_ctx_buffer_mapped;
-        struct ctx_header_desc ctx_header;
-};
-
 struct channel_gk20a_job {
         struct nvgpu_mapped_buf **mapped_buffers;
         int num_mapped_buffers;
@@ -190,7 +172,6 @@ struct channel_gk20a {
         int chid;
         bool wdt_enabled;
         nvgpu_atomic_t bound;
-        bool first_init;
         bool vpr;
         bool deterministic;
         /* deterministic, but explicitly idle and submits disallowed */
@@ -210,8 +191,6 @@ struct channel_gk20a {
 
         struct gpfifo_desc gpfifo;
 
-        struct channel_ctx_gk20a ch_ctx;
-
         struct nvgpu_mem inst_block;
 
         u64 userd_iova;
@@ -262,6 +241,8 @@ struct channel_gk20a {
         struct channel_t19x t19x;
 #endif
 
+        struct ctx_header_desc ctx_header;
+
         /* Any operating system specific data. */
         void *os_priv;
 };