diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-03-31 16:33:02 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-04-13 16:12:41 -0400 |
commit | 9b5427da37161c350d28a821652f2bb84bca360f (patch) | |
tree | 989e7b649b7b5e54d1d316b245b61c1881a15de6 /drivers/gpu/nvgpu/gk20a/channel_gk20a.c | |
parent | 2adf9164d9d68cc3ab700af84724034682f44ab8 (diff) |
gpu: nvgpu: Support GPUs with no physical mode
Support GPUs which cannot choose between SMMU and physical
addressing.
Change-Id: If3256fa1bc795a84d039ad3aa63ebdccf5cc0afb
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1120469
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/channel_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/channel_gk20a.c | 23 |
1 files changed, 11 insertions, 12 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c index 61211239..e8d82e0e 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c | |||
@@ -333,33 +333,32 @@ static int channel_gk20a_setup_userd(struct channel_gk20a *c) | |||
333 | return 0; | 333 | return 0; |
334 | } | 334 | } |
335 | 335 | ||
336 | static void channel_gk20a_bind(struct channel_gk20a *ch_gk20a) | 336 | static void channel_gk20a_bind(struct channel_gk20a *c) |
337 | { | 337 | { |
338 | struct gk20a *g = ch_gk20a->g; | 338 | struct gk20a *g = c->g; |
339 | struct fifo_gk20a *f = &g->fifo; | 339 | struct fifo_gk20a *f = &g->fifo; |
340 | struct fifo_engine_info_gk20a *engine_info = | 340 | struct fifo_engine_info_gk20a *engine_info = |
341 | f->engine_info + ENGINE_GR_GK20A; | 341 | f->engine_info + ENGINE_GR_GK20A; |
342 | 342 | u32 inst_ptr = gk20a_mm_inst_block_addr(g, &c->inst_block) | |
343 | u32 inst_ptr = gk20a_mem_phys(&ch_gk20a->inst_block) | ||
344 | >> ram_in_base_shift_v(); | 343 | >> ram_in_base_shift_v(); |
345 | 344 | ||
346 | gk20a_dbg_info("bind channel %d inst ptr 0x%08x", | 345 | gk20a_dbg_info("bind channel %d inst ptr 0x%08x", |
347 | ch_gk20a->hw_chid, inst_ptr); | 346 | c->hw_chid, inst_ptr); |
348 | 347 | ||
349 | ch_gk20a->bound = true; | 348 | c->bound = true; |
350 | 349 | ||
351 | gk20a_writel(g, ccsr_channel_r(ch_gk20a->hw_chid), | 350 | gk20a_writel(g, ccsr_channel_r(c->hw_chid), |
352 | (gk20a_readl(g, ccsr_channel_r(ch_gk20a->hw_chid)) & | 351 | (gk20a_readl(g, ccsr_channel_r(c->hw_chid)) & |
353 | ~ccsr_channel_runlist_f(~0)) | | 352 | ~ccsr_channel_runlist_f(~0)) | |
354 | ccsr_channel_runlist_f(engine_info->runlist_id)); | 353 | ccsr_channel_runlist_f(engine_info->runlist_id)); |
355 | 354 | ||
356 | gk20a_writel(g, ccsr_channel_inst_r(ch_gk20a->hw_chid), | 355 | gk20a_writel(g, ccsr_channel_inst_r(c->hw_chid), |
357 | ccsr_channel_inst_ptr_f(inst_ptr) | | 356 | ccsr_channel_inst_ptr_f(inst_ptr) | |
358 | ccsr_channel_inst_target_vid_mem_f() | | 357 | ccsr_channel_inst_target_vid_mem_f() | |
359 | ccsr_channel_inst_bind_true_f()); | 358 | ccsr_channel_inst_bind_true_f()); |
360 | 359 | ||
361 | gk20a_writel(g, ccsr_channel_r(ch_gk20a->hw_chid), | 360 | gk20a_writel(g, ccsr_channel_r(c->hw_chid), |
362 | (gk20a_readl(g, ccsr_channel_r(ch_gk20a->hw_chid)) & | 361 | (gk20a_readl(g, ccsr_channel_r(c->hw_chid)) & |
363 | ~ccsr_channel_enable_set_f(~0)) | | 362 | ~ccsr_channel_enable_set_f(~0)) | |
364 | ccsr_channel_enable_set_true_f()); | 363 | ccsr_channel_enable_set_true_f()); |
365 | } | 364 | } |
@@ -402,7 +401,7 @@ int channel_gk20a_alloc_inst(struct gk20a *g, struct channel_gk20a *ch) | |||
402 | return err; | 401 | return err; |
403 | 402 | ||
404 | gk20a_dbg_info("channel %d inst block physical addr: 0x%16llx", | 403 | gk20a_dbg_info("channel %d inst block physical addr: 0x%16llx", |
405 | ch->hw_chid, (u64)gk20a_mem_phys(&ch->inst_block)); | 404 | ch->hw_chid, gk20a_mm_inst_block_addr(g, &ch->inst_block)); |
406 | 405 | ||
407 | gk20a_dbg_fn("done"); | 406 | gk20a_dbg_fn("done"); |
408 | return 0; | 407 | return 0; |