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authorSam Payne <spayne@nvidia.com>2014-10-31 17:27:33 -0400
committerDan Willemsen <dwillemsen@nvidia.com>2015-03-18 15:11:56 -0400
commit8c6a9fd1151299697037d58f33cfa306d8ac5d87 (patch)
tree9bb909474f12565e7f61251b8b80f300030bde52 /drivers/gpu/nvgpu/gk20a/channel_gk20a.c
parent4f6dddcf78233b9939ee32c6f09519f27c3b8fb4 (diff)
Revert "gpu: nvgpu: GR and LTC HAL to use const structs"
This reverts commit 41b82e97164138f45fbdaef6ab6939d82ca9419e. Change-Id: Iabd01fcb124e0d22cd9be62151a6552cbb27fc94 Signed-off-by: Sam Payne <spayne@nvidia.com> Reviewed-on: http://git-master/r/592221 Tested-by: Hoang Pham <hopham@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Mitch Luban <mluban@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/channel_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/channel_gk20a.c13
1 files changed, 6 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
index 777d7ca9..9f2e0017 100644
--- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
@@ -28,7 +28,6 @@
28 28
29#include "debug_gk20a.h" 29#include "debug_gk20a.h"
30 30
31#include "gr_ops.h"
32#include "gk20a.h" 31#include "gk20a.h"
33#include "dbg_gpu_gk20a.h" 32#include "dbg_gpu_gk20a.h"
34#include "fence_gk20a.h" 33#include "fence_gk20a.h"
@@ -639,7 +638,7 @@ void gk20a_free_channel(struct channel_gk20a *ch, bool finish)
639 gk20a_free_error_notifiers(ch); 638 gk20a_free_error_notifiers(ch);
640 639
641 /* release channel ctx */ 640 /* release channel ctx */
642 g->ops.gr->free_channel_ctx(ch); 641 g->ops.gr.free_channel_ctx(ch);
643 642
644 gk20a_gr_flush_channel_tlb(gr); 643 gk20a_gr_flush_channel_tlb(gr);
645 644
@@ -1559,8 +1558,8 @@ int gk20a_submit_channel_gpfifo(struct channel_gk20a *c,
1559 1558
1560#ifdef CONFIG_DEBUG_FS 1559#ifdef CONFIG_DEBUG_FS
1561 /* update debug settings */ 1560 /* update debug settings */
1562 if (g->ops.ltc->sync_debugfs) 1561 if (g->ops.ltc.sync_debugfs)
1563 g->ops.ltc->sync_debugfs(g); 1562 g->ops.ltc.sync_debugfs(g);
1564#endif 1563#endif
1565 1564
1566 gk20a_dbg_info("channel %d", c->hw_chid); 1565 gk20a_dbg_info("channel %d", c->hw_chid);
@@ -2081,7 +2080,7 @@ static int gk20a_channel_zcull_bind(struct channel_gk20a *ch,
2081 2080
2082 gk20a_dbg_fn(""); 2081 gk20a_dbg_fn("");
2083 2082
2084 return g->ops.gr->bind_ctxsw_zcull(g, gr, ch, 2083 return g->ops.gr.bind_ctxsw_zcull(g, gr, ch,
2085 args->gpu_va, args->mode); 2084 args->gpu_va, args->mode);
2086} 2085}
2087 2086
@@ -2301,7 +2300,7 @@ long gk20a_channel_ioctl(struct file *filp,
2301 __func__, cmd); 2300 __func__, cmd);
2302 return err; 2301 return err;
2303 } 2302 }
2304 err = ch->g->ops.gr->alloc_obj_ctx(ch, 2303 err = ch->g->ops.gr.alloc_obj_ctx(ch,
2305 (struct nvgpu_alloc_obj_ctx_args *)buf); 2304 (struct nvgpu_alloc_obj_ctx_args *)buf);
2306 gk20a_idle(dev); 2305 gk20a_idle(dev);
2307 break; 2306 break;
@@ -2313,7 +2312,7 @@ long gk20a_channel_ioctl(struct file *filp,
2313 __func__, cmd); 2312 __func__, cmd);
2314 return err; 2313 return err;
2315 } 2314 }
2316 err = ch->g->ops.gr->free_obj_ctx(ch, 2315 err = ch->g->ops.gr.free_obj_ctx(ch,
2317 (struct nvgpu_free_obj_ctx_args *)buf); 2316 (struct nvgpu_free_obj_ctx_args *)buf);
2318 gk20a_idle(dev); 2317 gk20a_idle(dev);
2319 break; 2318 break;