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authorThomas Fleury <tfleury@nvidia.com>2016-03-15 22:06:43 -0400
committerTerje Bergstrom <tbergstrom@nvidia.com>2016-05-21 14:34:18 -0400
commit64f2e3ee9be32aab8bc7f3d373e4b89d60d3fe53 (patch)
tree83c8baae9c734630481d3dc9d4e46cc468284f33 /drivers/gpu/nvgpu/gk20a/channel_gk20a.c
parent57a59616b596d4d7b134ab8a32a4ab7cdfa15f3d (diff)
gpu: nvgpu: update trace for sched params
Use an inline function instead of a macro to "expand" all channel parameters. Jira EVLR-244 Jira EVLR-318 Change-Id: I4e8c5ee6bc9da36564af171be809f50dd2dfd439 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1150050 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/channel_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/channel_gk20a.c23
1 files changed, 12 insertions, 11 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
index 69da03e1..f70c4bb7 100644
--- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
@@ -1196,7 +1196,8 @@ static int __gk20a_channel_open(struct gk20a *g, struct file *filp)
1196 return -ENOMEM; 1196 return -ENOMEM;
1197 } 1197 }
1198 1198
1199 trace_gk20a_channel_sched_defaults(GK20A_TP_ARGS_SCHED(ch)); 1199 gk20a_channel_trace_sched_param(
1200 trace_gk20a_channel_sched_defaults, ch);
1200 1201
1201 filp->private_data = ch; 1202 filp->private_data = ch;
1202 return 0; 1203 return 0;
@@ -3060,8 +3061,8 @@ long gk20a_channel_ioctl(struct file *filp,
3060 gk20a_dbg(gpu_dbg_gpu_dbg, "setting timeout (%d ms) for chid %d", 3061 gk20a_dbg(gpu_dbg_gpu_dbg, "setting timeout (%d ms) for chid %d",
3061 timeout, ch->hw_chid); 3062 timeout, ch->hw_chid);
3062 ch->timeout_ms_max = timeout; 3063 ch->timeout_ms_max = timeout;
3063 3064 gk20a_channel_trace_sched_param(
3064 trace_gk20a_channel_set_timeout(GK20A_TP_ARGS_SCHED(ch)); 3065 trace_gk20a_channel_set_timeout, ch);
3065 break; 3066 break;
3066 } 3067 }
3067 case NVGPU_IOCTL_CHANNEL_SET_TIMEOUT_EX: 3068 case NVGPU_IOCTL_CHANNEL_SET_TIMEOUT_EX:
@@ -3075,8 +3076,8 @@ long gk20a_channel_ioctl(struct file *filp,
3075 timeout, ch->hw_chid); 3076 timeout, ch->hw_chid);
3076 ch->timeout_ms_max = timeout; 3077 ch->timeout_ms_max = timeout;
3077 ch->timeout_debug_dump = timeout_debug_dump; 3078 ch->timeout_debug_dump = timeout_debug_dump;
3078 3079 gk20a_channel_trace_sched_param(
3079 trace_gk20a_channel_set_timeout(GK20A_TP_ARGS_SCHED(ch)); 3080 trace_gk20a_channel_set_timeout, ch);
3080 break; 3081 break;
3081 } 3082 }
3082 case NVGPU_IOCTL_CHANNEL_GET_TIMEDOUT: 3083 case NVGPU_IOCTL_CHANNEL_GET_TIMEDOUT:
@@ -3095,8 +3096,8 @@ long gk20a_channel_ioctl(struct file *filp,
3095 ((struct nvgpu_set_priority_args *)buf)->priority); 3096 ((struct nvgpu_set_priority_args *)buf)->priority);
3096 3097
3097 gk20a_idle(dev); 3098 gk20a_idle(dev);
3098 3099 gk20a_channel_trace_sched_param(
3099 trace_gk20a_channel_set_priority(GK20A_TP_ARGS_SCHED(ch)); 3100 trace_gk20a_channel_set_priority, ch);
3100 break; 3101 break;
3101 case NVGPU_IOCTL_CHANNEL_ENABLE: 3102 case NVGPU_IOCTL_CHANNEL_ENABLE:
3102 err = gk20a_busy(dev); 3103 err = gk20a_busy(dev);
@@ -3182,8 +3183,8 @@ long gk20a_channel_ioctl(struct file *filp,
3182 ((struct nvgpu_runlist_interleave_args *)buf)->level); 3183 ((struct nvgpu_runlist_interleave_args *)buf)->level);
3183 3184
3184 gk20a_idle(dev); 3185 gk20a_idle(dev);
3185 3186 gk20a_channel_trace_sched_param(
3186 trace_gk20a_channel_set_runlist_interleave(GK20A_TP_ARGS_SCHED(ch)); 3187 trace_gk20a_channel_set_runlist_interleave, ch);
3187 break; 3188 break;
3188 case NVGPU_IOCTL_CHANNEL_SET_TIMESLICE: 3189 case NVGPU_IOCTL_CHANNEL_SET_TIMESLICE:
3189 err = gk20a_busy(dev); 3190 err = gk20a_busy(dev);
@@ -3197,8 +3198,8 @@ long gk20a_channel_ioctl(struct file *filp,
3197 ((struct nvgpu_timeslice_args *)buf)->timeslice_us); 3198 ((struct nvgpu_timeslice_args *)buf)->timeslice_us);
3198 3199
3199 gk20a_idle(dev); 3200 gk20a_idle(dev);
3200 3201 gk20a_channel_trace_sched_param(
3201 trace_gk20a_channel_set_timeslice(GK20A_TP_ARGS_SCHED(ch)); 3202 trace_gk20a_channel_set_timeslice, ch);
3202 break; 3203 break;
3203 case NVGPU_IOCTL_CHANNEL_SET_PREEMPTION_MODE: 3204 case NVGPU_IOCTL_CHANNEL_SET_PREEMPTION_MODE:
3204 if (ch->g->ops.gr.set_preemption_mode) { 3205 if (ch->g->ops.gr.set_preemption_mode) {