diff options
author | Haley Teng <hteng@nvidia.com> | 2016-04-21 09:02:14 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-05-09 12:52:04 -0400 |
commit | 4c4d0e6eb29fab7c1fb54cb7a7f5e3e41e245991 (patch) | |
tree | 258d1918e82725739932b8e16f7c4296178fae74 /drivers/gpu/nvgpu/gk20a/channel_gk20a.c | |
parent | f138e7f69d7918d597d2df34af1e1d0353ea2888 (diff) |
nvgpu: vgpu: create fifo.force_reset_ch in gpu_ops
gk20a_fifo_force_reset_ch() does not support vgpu now, so we need to
create a function pointer in gpu_ops and assign it differently for
vgpu and non-vgpu.
Bug 200184349
Change-Id: I5f8f4f731b4b970c4ff8de65531f25568e7691b6
Signed-off-by: Haley Teng <hteng@nvidia.com>
Reviewed-on: http://git-master/r/1130420
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/channel_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/channel_gk20a.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c index 0d7a6bec..189ec330 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c | |||
@@ -3114,10 +3114,10 @@ long gk20a_channel_ioctl(struct file *filp, | |||
3114 | __func__, cmd); | 3114 | __func__, cmd); |
3115 | break; | 3115 | break; |
3116 | } | 3116 | } |
3117 | /* enable channel */ | 3117 | if (ch->g->ops.fifo.enable_channel) |
3118 | gk20a_writel(ch->g, ccsr_channel_r(ch->hw_chid), | 3118 | ch->g->ops.fifo.enable_channel(ch); |
3119 | gk20a_readl(ch->g, ccsr_channel_r(ch->hw_chid)) | | 3119 | else |
3120 | ccsr_channel_enable_set_true_f()); | 3120 | err = -ENOSYS; |
3121 | gk20a_idle(dev); | 3121 | gk20a_idle(dev); |
3122 | break; | 3122 | break; |
3123 | case NVGPU_IOCTL_CHANNEL_DISABLE: | 3123 | case NVGPU_IOCTL_CHANNEL_DISABLE: |
@@ -3128,10 +3128,10 @@ long gk20a_channel_ioctl(struct file *filp, | |||
3128 | __func__, cmd); | 3128 | __func__, cmd); |
3129 | break; | 3129 | break; |
3130 | } | 3130 | } |
3131 | /* disable channel */ | 3131 | if (ch->g->ops.fifo.disable_channel) |
3132 | gk20a_writel(ch->g, ccsr_channel_r(ch->hw_chid), | 3132 | ch->g->ops.fifo.disable_channel(ch); |
3133 | gk20a_readl(ch->g, ccsr_channel_r(ch->hw_chid)) | | 3133 | else |
3134 | ccsr_channel_enable_clr_true_f()); | 3134 | err = -ENOSYS; |
3135 | gk20a_idle(dev); | 3135 | gk20a_idle(dev); |
3136 | break; | 3136 | break; |
3137 | case NVGPU_IOCTL_CHANNEL_PREEMPT: | 3137 | case NVGPU_IOCTL_CHANNEL_PREEMPT: |
@@ -3153,7 +3153,7 @@ long gk20a_channel_ioctl(struct file *filp, | |||
3153 | __func__, cmd); | 3153 | __func__, cmd); |
3154 | break; | 3154 | break; |
3155 | } | 3155 | } |
3156 | err = gk20a_fifo_force_reset_ch(ch, true); | 3156 | err = ch->g->ops.fifo.force_reset_ch(ch, true); |
3157 | gk20a_idle(dev); | 3157 | gk20a_idle(dev); |
3158 | break; | 3158 | break; |
3159 | case NVGPU_IOCTL_CHANNEL_EVENT_ID_CTRL: | 3159 | case NVGPU_IOCTL_CHANNEL_EVENT_ID_CTRL: |