gpu: nvgpu: Prune redundant cache maintenance

Remove redundant cache maintenance operations. Instance blocks and
graphics context buffers are uncached, so they do not need any cache
maintenance.

Bug 1421824

Change-Id: Ie0be67bf0be493d9ec9e6f8226f2f9359cba9f54
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/406948

1 files changed, 0 insertions, 17 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
index 00f8ac94..61938f8e 100644
--- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
@@ -128,8 +128,6 @@ int channel_gk20a_commit_va(struct channel_gk20a *c)
         gk20a_mem_wr32(inst_ptr, ram_in_adr_limit_hi_w(),
                 ram_in_adr_limit_hi_f(u64_hi32(c->vm->va_limit)));
 
-        gk20a_mm_l2_invalidate(c->g);
-
         return 0;
 }
 
@@ -159,8 +157,6 @@ static int channel_gk20a_commit_userd(struct channel_gk20a *c)
                  pbdma_userd_target_vid_mem_f() |
                  pbdma_userd_hi_addr_f(addr_hi));
 
-        gk20a_mm_l2_invalidate(c->g);
-
         return 0;
 }
 
@@ -183,9 +179,6 @@ static int channel_gk20a_set_schedule_params(struct channel_gk20a *c,
         /* preempt the channel */
         WARN_ON(gk20a_fifo_preempt_channel(c->g, c->hw_chid));
 
-        /* flush GPU cache */
-        gk20a_mm_l2_flush(c->g, true);
-
         /* value field is 8 bits long */
         while (value >= 1 << 8) {
                 value >>= 1;
@@ -209,8 +202,6 @@ static int channel_gk20a_set_schedule_params(struct channel_gk20a *c,
                 gk20a_readl(c->g, ccsr_channel_r(c->hw_chid)) |
                 ccsr_channel_enable_set_true_f());
 
-        gk20a_mm_l2_invalidate(c->g);
-
         return 0;
 }
 
@@ -277,8 +268,6 @@ static int channel_gk20a_setup_ramfc(struct channel_gk20a *c,
 
         gk20a_mem_wr32(inst_ptr, ram_fc_chid_w(), ram_fc_chid_id_f(c->hw_chid));
 
-        gk20a_mm_l2_invalidate(c->g);
-
         return 0;
 }
 
@@ -299,8 +288,6 @@ static int channel_gk20a_setup_userd(struct channel_gk20a *c)
         gk20a_mem_wr32(c->userd_cpu_va, ram_userd_gp_get_w(), 0);
         gk20a_mem_wr32(c->userd_cpu_va, ram_userd_gp_put_w(), 0);
 
-        gk20a_mm_l2_invalidate(c->g);
-
         return 0;
 }
 
@@ -649,8 +636,6 @@ void gk20a_free_channel(struct channel_gk20a *ch, bool finish)
         ch->gpfifo.cpu_va = NULL;
         ch->gpfifo.iova = 0;
 
-        gk20a_mm_l2_invalidate(ch->g);
-
         memset(&ch->gpfifo, 0, sizeof(struct gpfifo_desc));
 
 #if defined(CONFIG_GK20A_CYCLE_STATS)
@@ -1155,8 +1140,6 @@ static int gk20a_alloc_channel_gpfifo(struct channel_gk20a *c,
         channel_gk20a_setup_userd(c);
         channel_gk20a_commit_userd(c);
 
-        gk20a_mm_l2_invalidate(c->g);
-
         /* TBD: setup engine contexts */
 
         err = channel_gk20a_alloc_priv_cmdbuf(c);